Memory device

Abstract

A memory device includes memory cells each having a capacitor including a lower electrode, a ferroelectric film and an upper electrode which are formed in this order over a substrate made of silicon. The ferroelectric film is selectively grown on the lower electrode. Such selective formation of the ferroelectric film on the lower electrode having a desired shape prevents a damaged portion from occurring in the ferroelectric film, thus making it possible to downsize the memory cells.

Description

technical field [0001] The present invention relates to a memory device including a capacitor using a capacitor film made of a ferroelectric in a memory cell. Background technique [0002] Figure 5 A conventional memory device is shown in which a memory cell is composed of a capacitor using a ferroelectric in a capacitor film and a selection transistor that can selectively access the capacitor. Such as Figure 5 As shown, one electrode of the ferroelectric capacitor 101 is connected to the source of the selection transistor 102, and the other electrode is connected to a cell plate line CP. The drain of the selection transistor 102 is connected to the bit line BL, and the gate is connected to the word line WL. [0003] An example of the cross-sectional configuration of a memory cell having such a circuit configuration is given in Figure 6 Indicated. Such as Figure 6 As shown, the selection transistor 102 is composed of: a drain region 111 and a source region 112 formed...

AI Technical Summary

Problems solved by technology

[0012] In order to suppress the occurrence of such a damaged region 116a, recovery annealing for recovering the damaged region 116a is performed after the formation of the ferroelectric capacitor 101, but the effect of completely disappearing the damaged region 116a is not effective.

[0013] In addition, since the recovery annealing treatment temperature is approximately the same as the temperature at which the ferroelectric film 116 is crystallized, when the ferroelectric capacitor 101 is multi-layered, recovery annealing is required for each layer, which causes the Thermal Deterioration of Wiring

Therefore, it becomes difficult to realize a three-dimensional capacitor array in which two or more layers of ferroelectric capacitors 101 are stacked.

[0014] In addition, the manufacturing method of the prior art, in Figure 7 In the process shown in (a), the ferroelectric film 116 is formed on the entire surface of the first electrode forming film 115A by the sputtering method or the sol-gel method, and polycrystallization is necessary.

Therefore, it will cause the average of the direction in which the polarization appears due to the isotropy of the crystal direction, so that it is very difficult to control the crystal direction of the ferroelectric to the direction in which the polarization deviation is maximized.

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