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Compositions and methods for low downforce pressure polishing of copper

A composition and pressure technology, applied in polishing compositions containing abrasives, chemical instruments and methods, aqueous dispersants, etc., can solve problems such as affecting production capacity

Inactive Publication Date: 2005-07-27
ROHM & HAAS ELECTRONICS MATERIALS CMP HLDG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when the pressure is reduced, the production capacity is seriously affected

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] This test measures the rate at which large quantities of copper are polished from semiconductor wafers under low downforce. In particular, this test determines the effect of the addition of phosphorus-containing compounds on the polishing rate at 1 psi during the first polishing operation. Using Applied Materials, Inc. Mirra 200mm polisher and utilizing IC1010 TM A microporous polyurethane polishing pad (Rodel, Inc.) was used to planarize the sample under a downforce of about 1 psi (6.89 kPa) and a polishing fluid flow rate of 160 cc / min, a table speed of 80 RPM, and a carriage speed of 75 RPM. This sample is a 200 mm copper-clad (copper blanket) wafer. The pH of the polishing solution was adjusted to 2.8 with nitric acid. All solutions contained deionized water.

[0031] Table 1

[0032] test

Ammonium Phosphate (wt%)

Downforce (kPa)

Removal rate ( / min)

A

-

6.89

1500

1

0.10

6.89

...

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PUM

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Abstract

The present invention provides an aqueous composition useful for polishing copper on a semiconductor wafer at a down force pressure of at least less than 20.68 kPa, comprising by weight percent 1 to 15 oxidizer, 0.1 to 1 inhibitor for a nonferrous metal, 0.05 to 3 complexing agent for the nonferrous metal, 0.01 to 5 carboxylic acid polymer, 0.01 to 5 modified cellulose, 0.05 to 10 phosphorus-containing compound and 0 to 10 abrasive, wherein the phosphorus-containing compound increases removal of the copper.

Description

technical field [0001] The present invention relates to chemical mechanical planarization (CMP) of semiconductor wafer materials and more particularly, the present invention relates to CMP compositions and methods for polishing copper interconnects from semiconductor wafers in the presence of dielectric and barrier materials. Background technique [0002] A semiconductor wafer typically comprises a silicon wafer and a dielectric layer containing a plurality of trenches arranged within the dielectric layer to form a pattern of circuit interconnections. The arrangement of these patterns usually has a damascene structure or a dual damascene structure. The patterned dielectric layer is covered with a barrier layer and the barrier layer is covered with a metal layer. The metal layer has a thickness at least sufficient to allow metal to fill the pattern trenches to form circuit interconnections. [0003] CMP processes typically include multiple polishing steps. For example, the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B37/00C09G1/02C09G1/04C09K3/14C23F3/06H01L21/304H01L21/321
CPCC09G1/04C09G1/02H01L21/3212C23F3/06C09K3/14
Inventor W·B·戈德堡F·J·凯利J·匡西J·K·索T·M·托马斯王红雨
Owner ROHM & HAAS ELECTRONICS MATERIALS CMP HLDG INC
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