Grid and formation of fast-flashing memory therewith

Abstract

The method comprises: orderly forming a grid dielectric layer, a conducting layer, an isolation protective layer, a sacrificial layer and a patterned mask layer on a substrate; using the patterned mask layer as etching mask and using the isolation protective layer as etching stop layer to remove the exposed sacrificial layer, and then removing the patterned mask layer; forming a spacer on the sidewall of the sacrificial layer, and then using the spacer and the sacrificial layer as etching mask to remove the portion of isolation protective layer and conducting layer in order to form a grid; finally removing the sacrificial layer, spacer and isolation protective layer. The invention can avoid generation of edge and corner on the top surface of grid at the time of etching sacrificial layer.

Description

technical field [0001] The invention relates to a method for forming a semiconductor element, in particular to a method for forming a gate and a flash memory. Background technique [0002] With the continuous miniaturization of semiconductor components, the demand for how to improve the integration of components is becoming more and more urgent. Among them, the critical dimension of the semiconductor element is usually limited by the resolution of the lithography process, and the resolution of the lithography process depends on the wavelength of the light source (wavelength), so this will limit the pattern pitch of the semiconductor element to a fixed distance superior. If the distance between the patterns is smaller than the wavelength of the light source, it cannot be precisely patterned and defined. [0003] Therefore, a process that can increase the gate width to reduce the gate pitch has been developed, such as Figure 1A to Figure 1E shown. [0004] Figure 1A to Fi...

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Problems solved by technology

However, performing a chemical mechanical polishing process (CMP) complicates the process

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