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Semiconductor device and method for manufacturing the same

a semiconductor and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of mos transistor performance being remarkably degraded, fine transistors not being able to be formed, and damage to the silicon substrate b>101/b>, so as to prevent damage to the semiconductor substrate without excessively complicating the manufacturing process

Inactive Publication Date: 2005-04-07
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a method for manufacturing a semiconductor device with a buried conductive layer connected to a source / drain of a MOS transistor without damaging the substrate and without excessively complicating the manufacturing process. The method includes steps of forming a first insulating film on a semiconductor substrate, forming a first conductive film as a gate electrode and a second insulating film on the first insulating film, forming a third insulating film on the whole surface of the semiconductor substrate having the first insulating film, the first conductive film, and the second insulating film formed thereon, forming a first mask layer on the second conductive film, processing the first mask layer to have a pattern, selectively etching away the second mask layer, and selectively etching away the second conductive film with the patterns of the first and second mask layers as a mask. The method allows for a smaller interval of the patterns of the second conductive films, reducing the probability of the edge portion of the pattern being located on the associated side wall insulating film and promoting scale down of the semiconductor device. The first and second mask layers may be formed of either a conductive film or an insulating film.

Problems solved by technology

In such a way, the silicon substrate 101 will be damaged.
Such damage of the silicon substrate 101 results in the performance of the MOS transistor being remarkably degraded.
Hence, this results in the fine transistor not being able to be formed.
Therefore, the above-mentioned two methods for preventing the damage of the silicon substrate 101 are not suitable for practical use.
While the above-mentioned manufacturing method is suitable for the scale-down of the semiconductor device, the etching, by which the first contact hole is perforated, needs to be stopped at the time when the thickness of the insulating layer has been halved; hence, the control of the amount of etching is difficult to be carried out.

Method used

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  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same

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first embodiment

[0037] Referring first to FIGS. 3A to 3I, there are illustrated cross sectional views showing a semiconductor device according to the present invention and a method for manufacturing the same in order of process.

[0038] Firstly, as shown in FIG. 3A, a field oxide film 2 with about 400 nm thickness is formed in a region to be an isolation region of a P-type semiconductor silicon substrate 1 containing boron and having resistivity in the range of 1 to 12 Ω-cm by the well-known LOCOS method. Thereafter, a gate oxide film 3 with a thickness of 10 to 20 nm, or so, is formed on an active region, which is surrounded by the field oxide film 2, by the thermal oxidation method.

[0039] Then, after a polycrystalline silicon film about 100 nm thick containing phosphorus or arsenic of 2×1020 to 6×1020 atoms / cm3 is formed by the CVD method, a silicon oxide film 4 about 200 nm thick is formed on that polycrystalline silicon film by the CVD method. Thereafter, a photo resist film (not shown) is appli...

second embodiment

[0059] Next, a description will be given with respect to a semiconductor device according to the present invention and a method for manufacturing the same with reference to FIGS. 6A to 6E.

[0060] In the manufacturing process of the present embodiment, by carrying out the same process as that shown in FIGS. 3A to 3E in the first embodiment of the present invention, there is obtained a structure, as shown in FIG. 6A, having a pattern in which the silicon oxide film (the first mask layer) 12 is separated into portions, located on both sides of the gate electrode 5, with the width of the gate length.

[0061] Next, as shown in FIG. 6B, a silicon oxide film (a second mask layer) 51 about 200 nm thick is formed on the whole surface of the silicon substrate 1 by the CVD method.

[0062] Next, as shown in FIG. 6C, the silicon oxide film 51 is selectively etched away by the anisotropic dry etching so as to be left only on both side faces of the silicon oxide film 12.

[0063] Subsequently, the poly...

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Abstract

In a semiconductor device in which a source / drain and a wiring layer are connected to each other through an associated buried conductive layer, a separation width of the buried conductive layer on a upper portion of a gate electrode is made small to manufacture a highly reliable and fine MOS transistor. After a silicon oxide film has been formed on a first polycrystalline silicon film to be aligned with a width of a gate electrode, a second polycrystalline silicon film formed on the whole surface of a substrate is selectively etched away so as to be left only on both side faces of a pattern of the silicon oxide film. Thereafter, the first polycrystalline silicon film is selectively etched away with both the silicon oxide film and the second polycrystalline silicon film as an etching mask so that the first polycrystalline film is separated with a width which is smaller than that of the gate electrode by a width of a pattern of the second polycrystalline silicon film. As a result, the buried conductive layer including the first and second polycrystalline silicon films is formed.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Continuation of application Ser. No. 09 / 008,497 filed on Jan. 16, 1998. application Ser. No. 09 / 008,497 claims priority to Japanese Application 07-319482 filed on Nov. 14, 1995. application Ser. No. 09 / 008,497 is a Division of application Ser. No. 08 / 747,928 filed on Nov. 12, 1996. The contents of each of these applications are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and to a method for manufacturing the same. More particularly, it relates to a semiconductor device having a buried conductive layer which is connected to a source / drain of MOS transistor and extends over a gate electrode of the MOS transistor, and to a method for manufacturing the same. [0004] 2. Description of the Related Art [0005] In recent years, as high integration and scale-down (i.e., shrinking) of a semiconductor device have pro...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L21/336H01L21/763
CPCH01L21/763H01L29/6659H01L2924/0002Y10S257/90H01L2924/00
Inventor INOUE, HIROYUKI
Owner UNITED MICROELECTRONICS CORP
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