Method for fabrication of semiconductor device

Abstract

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I / Os and also including the step of forming redistribution layer for redistribution at least some of the Area I / Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to logic arrays and fabrication method for custom integrated circuit [0003] 2. Discussion of Background Art [0004] Semiconductor manufacturing is known to improve device density in exponential manner over time, but such improvements do come with a price. The cost of mask set required for each new process technology has been increasing exponentially. In addition, the minimum fabrication quantity due to the increases of wafer size has also increased exponentially at the same time. [0005] These changes represent an increasing challenge primarily to custom products, which tend to target smaller volume and less diverse market, therefore making the increased cost of product development and reduction of manufacturing flexibility very hard to accommodate. [0006] Custom Integrated Circuits can be segmented into two groups. The first are devices that have all their layers custom made. The second ...

AI Technical Summary

Benefits of technology

[0014] The present invention seeks to provide a new method for semiconductor device fabrication that is highly desirable for custom products. The current invention suggests the use of direct-write e-Beam in conjunction with a continuous logic array. The continuous array utilizes area I / O with area pads to allow variable sizing of designs and placing them on a wafer with various numbers of repetitions. The current invention provides solution to the challenge of high cost of mask-set and low flexibility that exist in the currently-common method of semiconductor fabrication. An additional advantage of the invention that it reduces the high cost of manufacturing the many different mask sets required in order to provide acceptable range of master slices. The current invention improves upon the prior art in many respects, including the way the semiconductor device is structured and those related to methods of fabrication of semiconductor devices.

[0015] The prior art reflected the motivation to better fit the device size to the custom application and therefore saving on wasted silicon. The current invention reflects the motivation to save the cost of mask with respect to the investment that would have been otherwise required to put in place proper set of master slices. The current invention also seeks to provide the ability to incorporate memory block in the custom device. The current invention provides a method to customize the device with respect the amount of logic and memory required.

[0016] The main point of the current invention is the use of area I / O to provide a continuous fabric that provides a continuous terrain of logic and I / O and also provides the ability to mix in continuous terrain of memory with islands of special functions like PLL and SERDES. The current invention shows that with area I / O and redistribution layer to connect the area I / O to area pads, many of the limitation of the prior art are overcome. A greater level of flexibility is therefore provided. The current invention also suggests to utilize Module Array, whereby additional layers such as Metal-1 and Metal-2 are generic and would be part of such borderless continuous terrain. Furthermore, the current invention also suggests the use of segmented routing whereby some of the connectivity layers are also generic and would be a part of the continuous terrain. In such fabric only few layers need to be customized while most of the layers are generic and consist primarily of a repeating pattern. A favorable embodiment of the current invention is a continuous terrain customizable by single custom via layer. Furthermore, the current invention suggests the use of direct-write e-Beam for those few custom layers. An added advantage of the current invention is the use of direct-write e-Beam on the continuous terrain to provide on the same wafer different product types, with different amount of product units of the various product types. The very large size of current wafer allows hundreds of device units, each of different type, built on a single wafer. Therefore the current invention allows to provide “on-demand” semiconductor device manufacturing, where one customers could get few units of one type of device for prototype work, while another may get few hundreds of devices for low volume production, all from a single wafer fabrication process.

[0017] To allow such level of flexibility with borderless terrain, the current invention suggests wafer level customization using equipment like direct-write e-Beam and dicing the wafer using highly flexible dicing using equipment like laser-based dicing. Such equipment allows mix and match of various die sizes on the wafer, as opposed to the saw dicing commonly used in the industry, which requires dicing along complete straight lines from one wafer edge to the other. An added advantage of the current invention's is the use of area pads and homogenous pad terrain so single probe card could be use for various devices.

[0018] The present invention also seeks to provide an improved semiconductor device including borderless logic array; area I / Os; and a redistribution layer for redistributing at least some of the area I / Os.

[0019] Preferably some of the pads are used to connect the semiconductor device to other devices and overlays at least a portion of the logic array or a portion of the area I / Os.

Problems solved by technology

Semiconductor manufacturing is known to improve device density in exponential manner over time, but such improvements do come with a price.

The cost of mask set required for each new process technology has been increasing exponentially.

These changes represent an increasing challenge primarily to custom products, which tend to target smaller volume and less diverse market, therefore making the increased cost of product development and reduction of manufacturing flexibility very hard to accommodate.

Yet, it is always a challenge to come up with minimum set of Master Slices that will provide a good fit for maximal number of designs.

The difficulty to provide variable-sized devices is due to the need of providing I / O cells and associated pads to connect the device to the package.

This method presents a severe limitation on the I / O cell to use the same transistors as used for the logic and would not allow the use of higher operating voltage for the I / O.

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