MOS transistor and method of manufacturing the same

Abstract

In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that is spaced apart from the first insulating layer. A lightly doped source / drain region is formed in the surface portions of the substrate between the second insulating layer and the gate structure. A source / drain extension layer are formed on the lightly doped source / drain region. A heavily doped source / drain region is formed on the second insulating layer so as to connect with the source / drain extension layer. The short channel effect is suppressed and the source / drain junction capacitance is reduced.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10 / 440,354, filed on May 15, 2003, now pending, which is claims priority from Korean Patent Application 2002-65649 filed on Oct. 26, 2002, the contents of which are herein incorporated by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device capable of suppressing a short channel effect and reducing a source / drain junction capacitance, and a method of manufacturing the same. [0004] 2. Description of the Related Art [0005] As semiconductor devices are developed having a high degree of integration, an active region becomes smaller in size. Thus, a gate length of a MOS transistor formed on the active region becomes shorter. As the gate length decreases, the influence of the source...

AI Technical Summary

Benefits of technology

[0012] The invention solves the aforementioned problems and accordingly, it is a first object of the invention to provide a MOS transistor capable of suppressing the short channel effect and decreasing the source / drain junction capacitance.

[0013] It is a second object of the invention to provide a method of manufacturing a MOS transistor capable of suppressing the short channel effect and decreasing the source / drain junction capacitance.

[0015] Furthermore, according to another embodiment of the invention, a gate structure is formed on a semiconductor substrate, the gate structure including a gate insulating layer and a gate electrode stacked on the gate insulating layer. A first insulating layer is formed on the top and the sides of the gate structure. Second insulating layers are formed on the substrate and are spaced apart from the first insulating layer. Lightly doped source / drain regions are formed in the surface portions of the substrate between the gate structure and the second insulating layers. Heavily doped source / drain regions are formed on the second insulating layers so as to fill gaps between the gate structure and the second insulating layers.

[0018] Furthermore, according to another embodiment of the invention, a gate structure in which a gate insulating layer and a gate electrode are successively stacked is formed on a semiconductor substrate, and then, a first insulating layer is formed on the top and the sides of the gate structure. Second insulating layers are formed on the substrate to be spaced apart from the first insulating layer. An impurity is ion-implanted in the surface portions of the substrate between the gate structure and the second insulating layers, thereby forming lightly doped source / drain regions. Then, heavily doped source / drain regions are formed on the second insulating layers so as to fill gaps between the gate structure and the second insulating layers.

[0019] According to embodiments of the invention, a channel region and the lightly doped source / drain regions (i.e., LDD regions) are formed in the surface of the semiconductor substrate, while the heavily doped source / drain regions are formed on the insulating layer, thereby obtaining the MOS transistor having the similar structure to that of the SOI transistor and performing the same operation as that of a transistor formed on a bulk silicon substrate. So the short channel effect is suppressed and the source / drain junction capacitance is decreased, resulting in the improvement in the operating speed of the device.

Problems solved by technology

In addition to lowering the threshold voltage, a “punchthrough effect” between the source / drain is a severe problem accompanying the short channel effect.

However, as the source / drain junction depth becomes shallower, it becomes more difficult to apply the salicide process.

Therefore, a layer of accumulated holes is formed at the interface in the rear of the SOI layer, thereby generating floating body effects such as parasitic bipolar breakdown, latch-up, etc.

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