Silicon wafer support fixture with roughended surface

Abstract

A silicon-based wafer support tower particularly useful for batch-mode thermal chemical vapor deposition. The surfaces of the silicon tower are bead blasted to introduce sub-surface damage, which produces pits and cracks in the surface, which anchor subsequently deposited layer of, for example, silicon nitride, thereby inhibiting peeling of the nitride film. The surface roughness may be in the range of 0.25 to 2.5 μm. Wafer support portions of the tower are preferably composed of virgin polysilicon. The invention can be applied to other silicon parts in a deposition or other substrate processing reactor, such as tubular sleeves and reactor walls. Tubular silicon members are advantageously formed by extrusion from a silicon melt.

Description

RELATED APPLICATION [0001] This application is a division of Ser. No. 09 / 860,392, filed May 18, 2001 and to be issued on Sep. 19, 2006 as U.S. Pat. No. 7,108,746, incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates generally to semiconductor processing. In particular, the invention relates to wafer support fixtures used in batch-mode chemical vapor deposition. [0004] 2. Background Art [0005] The fabrication of silicon integrated circuits typically involves one or more steps of chemical vapor deposition (CVD). Many advanced deposition processes use plasma enchanced CVD to activate the chemical reaction resulting in the deposition of the film from a precursor gas. The plasma process allows low temperature deposition. On the other hand, thermal CVD is performed at elevated temperatures to thermally activate the chemical reaction resulting in the deposition of the film from a precursor gas. The temperatures associate...

AI Technical Summary

Problems solved by technology

However, thermal CVD tends to coat all surfaces exposed in the furnace.

However, as the feature sizes on integrated circuits has decreased to 0.18 μm and even smaller, quartz support towers have nonetheless experienced substantial problems with producing particles.

These particulates fall on the wafer and can significantly reduce the yield of operable integrated circuit dies obtained from the wafer.

However, after some number of runs, the number of particles greatly increases to a totally unacceptable level.

It is believed that the origin of the problem is that the silicon nitride is also depositing on the quartz tower.

Although quartz towers are relatively inexpensive, such short life greatly increases the cost of ownership (COO) when measured per wafer.

Also, the necessity of changing out towers and cleaning towers complicates the work flow and reduces productivity.

Both factors reduce the yield of operable dice obtained from the wafers.

However, the CVD silicon carbide film is fragile, and a single pin hole through the film ruins the coating protect so the tower must be scrapped.

Entire towers of CVD silicon carbide can be made, but they are very expensive.

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