Single-poly non-volatile memory device and its operation method

Abstract

A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of U. S. provisional application No. 60 / 597,210, filed Nov. 17, 2005.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to single-poly non-volatile memory (NVM) devices. More particularly, the present invention relates to single-poly electrical programmable read only memory (EPROM) devices, and program, read and erase methods for operating such device. [0004] 2. Description of the Prior Art [0005] Non Volatile Memory (NVM) is arguably one of the most popular electronic storage mediums. The basic conception is the memory, which retains data stored to it when powered off. This memory family has several members (ROM, OTP, EPROM, EEPROM, flash) with varying degrees of flexibility of use differentiating them. [0006] Depending on the times of program and erase operations of a memory, the NVM can be further cataloged into multi-time programmable memory...

AI Technical Summary

Benefits of technology

[0020] It is one object of the present invention to provide a single-poly, P-channel non-volatile memory unit that is compatible with advanced nano-scale semiconductor process.

Problems solved by technology

The stacked gate structure of non-volatile memory makes the advanced logic process more complex and more costly because additional polysilicon deposition, thermal budget, and difficult lithograph and etching steps are involved.

It is very hard to turn back to the original target one for the embedded nonvolatile memory process.

And moreover, the re-adjustment of the logic devices may seriously delay the product developing time schedule.

First, the prior art single-poly floating gate non-volatile memory unit occupies larger chip area.

Hitherto, the miniaturization of single-poly floating gate non-volatile memory unit for advanced 90-nano or below semiconductor process is still a huge challenge for the semiconductor manufacturers.

The shrunk gate oxide thickness impedes the development of the floating gate based single-poly MTP memory because thin tunnel oxide will affect long term charge retention, while increasing tunnel oxide thickness is not compatible with logic process.

Operating at high voltages also adversely affects the reliability of thin gate dielectric having a thickness of 50˜60 angstroms in the peripheral logic transistors if we don't want to introduce additional high voltage processes.

Further, conventional single-poly floating gate EPROM technology needs a large cell size and a high voltage to capacitively couple the floating gate for programming the memory cell.

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