Electrical and thermal contact for use in semiconductor devices and corresponding methods

Abstract

A contact for use with a memory element of a semiconductor device structure includes a conductive element and a thermal insulator component. The conductive element establishes an electrical path to the memory element, while the thermal insulator component thermally insulates the memory element. The thermal insulator component may reduce an amount of current required to change a conductivity state of the memory element, particularly when the memory element includes a so-called “phase change” element. Methods for fabricating such contacts are also disclosed.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of application Ser. No. 09 / 189,098, filed Nov. 9, 1998, pending. The disclosure of the previously referenced U.S. patent application referenced is hereby incorporated by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to an electrical and thermal contact for use in semiconductor devices. Particularly, the present invention relates to an electrical and thermal contact which reduces the amount of energy input that is required in order to switch a semiconductor device structure that is contacted thereto between two or more states. More specifically, the electrical and thermal contact of the present invention includes thin conductive layers which envelop an insulator component. The electrical and thermal contact is particularly useful for switching contacted structures that include a phase change component between two or more states...

AI Technical Summary

Benefits of technology

[0014] Fabricating the electrical and thermal contact includes forming a dielectric layer around the lateral peripheral portions of a semiconductor device structure to be contacted, patterning the dielectric layer to expose at least a portion of the semiconductor device structure to be contacted, such as an active device region thereof, depositing a first thin conductive layer, depositing another dielectric layer adjacent the first thin conductive layer, patterning the dielectric layer to define a thermal insulator component, depositing a second thin conductive layer adjacent the thermal insulator component and in electrical communication with the first thin conductive layer, and patterning the first and second thin conductive layers to define the intermediate conductive layer and the contact layer, respectively. The dielectric layer is fabricated from an electrically and thermally conductive material. Preferably, during patterning of the dielectric layer, the first thin conductive layer is utilized as an etch stop. The processes that may be employed to fabricate the electrical and thermal contact facilitate the fabrication of a relatively small electrical and thermal contact when compared with conventional metal contacts.

Problems solved by technology

Nevertheless, the application of too great a current to memory elements, such as fuse and antifuse elements, increases the potential that various other components of the EEPROM of which they are a part, including without limitation the gate oxide layer, transistors, and other structures on the surface thereof, may be damaged.

As noted previously, programming pulses which comprise high electrical voltages may damage various components of an EEPROM, including, without limitation, the gate oxide layer, transistors and other structures on the surface of the EEPROM.

Further, due to the high rate at which many conventional metal contacts dissipate heat, such contacts may necessitate the input of even greater amounts of current in order to adequately heat and activate an antifuse element.

Moreover, the typical use of conventional, relatively large metal contacts on such EEPROMs is somewhat undesirable from the standpoint that such contacts consume a great deal of surface area or “real estate” on the surface of the semiconductor device.

Thus, conventional metal contacts limit the density of active device regions on the semiconductor device.

The dissipation of heat away from the memory cell through the metal contact is especially undesirable when the memory cell includes a phase change component, such as a chalcogenide material layer, such as the EEPROM devices disclosed in U.S. Pat. No. 5,789,758 (hereinafter “the '758 Patent”), which issued to Alan R. Reinberg on Aug. 4, 1998.

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