Visual device, interlocking counter, and image sensor

Abstract

A visual device including plurality of array operation units arranged in a shape of a two-dimensional lattice, wherein each of the calculation data in each of the array operation units is transmitted counter-clockwisely between plurality of the array operation units arranged in a shape of a two-dimensional lattice.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This is a continuation of U.S. application Ser. No. 10 / 471,555, filed Sep. 12, 2003. This application relates to and claims priority from Japanese Patent Application No. 2001 / 69886, filed Mar. 13, 2001, No. 2001 / 134921, filed May 2, 2001, No. 2001 / 160172, filed May 29, 2001, No. 2001 / 176755, filed Jun. 12, 2001, No. 2001 / 229174, filed Jul. 30, 2001, No. 2001 / 321614, filed Oct. 19, 2001 and No. 2001 / 388967, filed Dec. 21, 2001. The entirety of the contents and subject matter of all of the above is incorporated herein by reference.FIELD OF THE INVENTION [0002] The present invention relates to a visual device searching and recognizing an object, whose array operation units and virtual array operation units carry out local and parallel image processing like a geometrical analysis means and so on, wherein an image sensor comprises a data processing device which consists of these array operation units and virtual array operation units, an inte...

AI Technical Summary

Benefits of technology

[0042] The invention described in claim 16 is an interlocked counter according to claim 13 or 14, which comprises a synchronous oscillator comprising: a flip-flop circuit for synchronous signal, a synchronous signal amplifier, a loop filter, a voltage controlled oscillator, and at least one logic gate for amplifying clock signal, wherein said latch circuit for synchronous signal memorizes said enable signal, said synchronous signal amplifier amplifies an output of said latch circuit for synchronous signal, said loop filter reduces a noise included in an output of said synchronous signal amplifier, said voltage controlled oscillator generates said clock signal, said voltage controlled oscillator changes phase of said clock signal according to voltage outputted by said loop filter, and at least one said logic gate for clock signal amplifies said clock signal. The present invention uses a D-flip-flop as said flip-flop circuit for synchronous signal, and said enable signal is inputted at a D terminal of said D-flip-flop. Note that said clock signal is inputted at a clock terminal of said D-flip flop. Therefore, said D-flip-flop circuit for synchronous signal memorizes the same signal as said enable signal. An amplifier possible to generate voltage necessary to control said voltage controlled oscillator is used as said synchronous signal amplifier. If this voltage is within a gate level, a NOT gate and a buffer is used as said synchronous signal amplifier. Otherwise, a general amplifier is used as said synchronous signal amplifier. A lag filter, a lag lead filter and

Problems solved by technology

The visual device, however, has mainly four problems.

First, a figure/ground separation means needs huge computational complexity, in order for nonlinear oscillators to separate at least one object area and a background area.

Therefore, these means heavily hindered from manufacturing of a high-performance image sensor comprising the visual device.

This is a factor that computational complexity of the figure/ground separation means increases.

However, since these transform methods not only process an image exactly but also carry out global processing, implementation of a visual device by hardware is not suitable.

By the way, there are four problems on a past array operation unit.

In this way, however, even though the controller communicates asynchronously, the processor must waste time in vain.

Second, it is difficult to distinguish a calculation datum before transmitting and a calculation datum after transmitting because order of transmitting the calculation data is irregular.

This cause is that all array operation units work independently.

Third, in a case that a calculation datum is transmitted toward three directions simultaneously, a processor does not always succeed in writing the calculation datum to its controller.

Fourth, in a case that a calculation datum is transmitted toward three directions simultaneously, it is difficult for an array operation unit received the calculation datum to distinguish two array operation units which are designated by transmission times in a horizontal direction and transmission times in a vertical

Images