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Visual device, interlocking counter, and image sensor

Inactive Publication Date: 2008-01-31
ECCHANDES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0632] As suggested by claim 5, the present invention can detect position and size of objects from a formed edge-information image 115, by carrying out processing every pixel, in parallel. In addition, the present invention can derive form of the objects even though it does not know the size and inclination of the objects beforehand. Since the visual device 2 is also used for preprocessing for recognizing some objects from a frame image of an animation image taken by a video camera, or from a still image taken by a digital camera or captured by a scanner, the visual device 2 can realize a pattern recognition device for the animation image and the still image quickly and cheaply. By outputting 36 or more of transfer-source inclination-redundant information 187, a system inputting a transfer-source inclination-redundant-information image 188 from the present invention can extract size of objects from the transfer-source inclination-redundant-information image 188, if desired.
[0633] As suggested by claim 6, the present invention can detect position and size of objects from a formed edge-information image 115, by carrying out processing every pixel, in parallel. In addition, the present invention can derive form of the objects even though it does not know the size and inclination of the objects beforehand. Since the visual device 2 is also used for preprocessing for recognizing some objects from a frame image of an animation image taken by a video camera, or from a still image taken by a digital camera or captured by a scanner, the visual device 2 can realize a pattern recognition device for the animation image and the still image quickly and cheaply. Since the array operation unit 100 outputs only a detection result, a system inputting the detection result from the present invention can make its communication mechanism simple.
[0634] As suggested by claim 7, the present invention can separate at least one object area 141 segmented by a binary image from a background area more quickly than separation of the past visual device 2 because each nonlinear oscillator inputs redundant-information 131 as an external noise. Therefore, a designer of an image sensor 251 can design a fast image sensor 251.
[0635] As suggested by claim 8 and claim 9, the array operation unit 100 transmits calculation data received in only at most two directions. Moreover, many of the calculation data have only to be transmitted in one direction. In short, when the processor 101 writes the calculation datum to the controller 103, a probability that the processor 101 is waited by the controller 103 becomes low. In addition, since the array operation unit 100 can distribute transmission load of the calculation data, the array operation unit 100 can transmit the calculation data efficiently.
[0636] As suggested by claim 10 and claim 11, the virtual array operation unit 105 transmits calculation data received in only at most two directions. Moreover, many of the calculation data have only to be transmitted in one direction. In short, when the processor 101 writes the calculation datum to the controller 103, a probability that the processor 101 is waited by the controller 103 becomes low. Moreover, the more the number of the array operation units 100 included in the virtual array operation unit 105 becomes, the more times the processor 101 does not write the calculation data to the controller 103. Therefore, the virtual array operation unit 105 can transmit the calculation data efficiently.
[0638] As suggested by claim 13 to claim 16, even though the interlocked counter 401 inputted some interlocking signals whose phase is different from each other, the interlocked counter 401 selects the latest phase of the signal from the signals, followed by generating its interlocking signal. Moreover, it can also output the count number synchronized with the phase of the interlocking signal. Therefore, even though some interlocked counters 401 were distributed in a whole of an LSI (Large Scale Integrated Circuit), the phases of interlocking signals of all interlocked counters 401 coincide with the latest one if all interlocked counters 401 communicate their interlocking signals with each other. Moreover, the count numbers of the interlocked counters 401 coincide with each other. Since the count numbers become divided signals of the clock signal, the interlocked counters 401 can supply the same divided signal to a whole of the LSI. On the other hand, since the LSI becomes large and the clock signal becomes fast, recently, reduction of power consumption of the LSI is desired. Therefore, an LSI designer must control the clock finely every part of the LSI. However, because of appearance of propagation delay time caused by long wiring and a problem of clock skew, it has been difficult for the LSI designer to carry out timing design even though he divided the clock signal. By using the present invention, then, the LSI designer can design an LSI corresponding to a high-frequency clock signal easily.
[0640] As suggested by claim 18 and claim 19, the higher the resolution of the image sensor 251 becomes, the much less than the number of pixels of the image sensor 251 the number of pixels in a sensor module 252 becomes, by increasing the number of the sensor modules 252. Therefore, a designer of the image sensor 251 can design the sensor module 252 easily. In addition, the manufacturer of the image sensor 251 can make the image sensor 251 in a high yield, in a short time, by arranging only sensor modules 252 already checked on a substrate, using LSI stacking technology. Therefore, an LSI designer can make an image sensor 251, the number of whose pixels is 100 million or more, that is, the number is equal to a human retina. In addition, an enforcement form of the image sensor 251 corresponding to the present invention can take out all pixel signals in a shorter time than a time of a general image sensor 251. Moreover, the enforcement form desires the less number of signal lines than the number of lines in a pixel-parallel image sensor 251. In the visual device 2, therefore, some virtual array operation units 105 arranged in the shape of a lattice can receive the necessary number of pixel signals in a short time, respectively, by using an enforcement form of the image sensor 251 corresponding to the present invention.
[0641] As suggested by claim 20, influence of noise on the image sensor 251 can be reduced because wiring length of signal lines between a sensor module 252 and the corresponding A / D converter 204 becomes short. In particular, in a case of the invention according to claim 20, total wiring length of signal lines between a sensor module 252 and the corresponding A / D converter 204, and signal lines between a A / D converter 204 and the corresponding digital circuit 402 becomes short. Moreover, they do not cross each other. Therefore, the maximum influence of noise on the image sensor 251 can be reduced. In addition, the number of A / D converters 204 is equal to the number of sensor modules 252. Therefore, even though the number of pixels of the image sensor 251 became big, a designer of the image sensor 251 can reduce the number of the A / D converters 204, by increasing the number of photo-receptor elements 261 in the sensor module 252. The designer of the image sensor 251, thus, can design a high-resolution image sensor 251, by increasing the number of bits of a digital signal outputted by the A / D converter 204. In addition, an LSI manufacturer can make an image sensor 251, the number of whose pixels is 100 million or more, which can stimulate human optic nerve directly, in parallel.

Problems solved by technology

The visual device, however, has mainly four problems.
First, a figure / ground separation means needs huge computational complexity, in order for nonlinear oscillators to separate at least one object area and a background area.
Therefore, these means heavily hindered from manufacturing of a high-performance image sensor comprising the visual device.
This is a factor that computational complexity of the figure / ground separation means increases.
However, since these transform methods not only process an image exactly but also carry out global processing, implementation of a visual device by hardware is not suitable.
By the way, there are four problems on a past array operation unit.
In this way, however, even though the controller communicates asynchronously, the processor must waste time in vain.
Second, it is difficult to distinguish a calculation datum before transmitting and a calculation datum after transmitting because order of transmitting the calculation data is irregular.
This cause is that all array operation units work independently.
Third, in a case that a calculation datum is transmitted toward three directions simultaneously, a processor does not always succeed in writing the calculation datum to its controller.
Fourth, in a case that a calculation datum is transmitted toward three directions simultaneously, it is difficult for an array operation unit received the calculation datum to distinguish two array operation units which are designated by transmission times in a horizontal direction and transmission times in a vertical direction of the calculation datum, where the transmission times in each direction designating the array operation units are equal to each other.
In this way, however, transmission efficiency is bad because a calculation datum of an array operation unit whose priority is low has not been transmitted until the calculation datum of the array operation unit whose priority is high is inputted.
Suppose, however, that a designer tries to design such an array operation circuit in practice, hardware complexity of the array operation unit becomes huge.
On the other hand, as concerns processing speed of the LSI, the more the frequency of a clock signal becomes, the serious the problems on clock skew and propagation delay time of signals becomes.
In a case that there are many PLLs in the LSI, however, it is impossible to coincide phases of all PLLs because of propagation delay time of the reference signal.
In addition, two PLLs can not communicate their comparison signals with each other.
Therefore, both PLLs generate a big jitter of their comparison signals.
Of course, a clock signal generated by the PLL generates a fatal jitter.
By the way, there is a problem that it is difficult for three-dimensional LSI technology to increase the number of vertical signal lines, while the three-dimensional LSI technology can increase the number of transistors.
Moreover, the transistors can not be arranged at a place where the vertical lines are arranged.
In short, the designer of the image sensor can not increase the number of pixels of the image sensor easily.

Method used

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  • Visual device, interlocking counter, and image sensor
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  • Visual device, interlocking counter, and image sensor

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Embodiment Construction

[0190] Some enforcement forms of a visual device 2 are shown below. With reference to the drawings, then, it is explained about the enforcement forms.

[0191] First, as shown in FIG. 1, an enforcement form of a visual device 2 corresponding to the invention described in claim 1 detects position, size and form of at least one object from the object moving in digital images 111, by using an image memorization means 12, an edge-information generation means 14, an edge-information formation means 15 and a geometrical analysis means 37. The image memorization means 12 memorizes the digital images 111 in order. The edge-information generation means 14 generates a rough edge-information image 113 including rough edge information 112 of at least one object moving in the digital images 111, by using two digital images 111. The edge-information formation means 15 forms the rough edge-information image 113 into a formed edge-information image 115, by using one of two digital images 111. The geo...

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Abstract

A visual device including plurality of array operation units arranged in a shape of a two-dimensional lattice, wherein each of the calculation data in each of the array operation units is transmitted counter-clockwisely between plurality of the array operation units arranged in a shape of a two-dimensional lattice.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This is a continuation of U.S. application Ser. No. 10 / 471,555, filed Sep. 12, 2003. This application relates to and claims priority from Japanese Patent Application No. 2001 / 69886, filed Mar. 13, 2001, No. 2001 / 134921, filed May 2, 2001, No. 2001 / 160172, filed May 29, 2001, No. 2001 / 176755, filed Jun. 12, 2001, No. 2001 / 229174, filed Jul. 30, 2001, No. 2001 / 321614, filed Oct. 19, 2001 and No. 2001 / 388967, filed Dec. 21, 2001. The entirety of the contents and subject matter of all of the above is incorporated herein by reference.FIELD OF THE INVENTION [0002] The present invention relates to a visual device searching and recognizing an object, whose array operation units and virtual array operation units carry out local and parallel image processing like a geometrical analysis means and so on, wherein an image sensor comprises a data processing device which consists of these array operation units and virtual array operation units, an inte...

Claims

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Application Information

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IPC IPC(8): G06K9/00G06T1/20G06F15/80G06T7/00G06V10/24G06V10/32H04N5/374
CPCG06K9/00234G06K9/00986G06K9/32G06K9/42G06T7/0044H04N5/232H03K21/38H03K21/406H04N3/1512H04N3/1537H04N3/1593G06T2207/30201G06T7/74G06V40/162G06V10/955G06V10/24G06V10/32H04N23/665H04N25/79H04N25/76H04N25/73
Inventor AJIOKA, YOSHIAKI
Owner ECCHANDES
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