Fabricating method of silicon layer with high resistance
a technology of silicon layer and fabrication method, which is applied in the direction of basic electric elements, electrical apparatus, and semiconductor devices, can solve the problems of poor reliability of devices containing these silicon layers, large variations of etc., and achieve the effect of increasing the total resistance of the silicon layer, improving the reliability of devices containing the silicon layer of invention, and increasing the conductivity between silicon layers
Inactive Publication Date: 2008-02-28
UNITED MICROELECTRONICS CORP
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Benefits of technology
The present invention provides a silicon layer with high resistance and a fabricating method to improve the reliability of devices containing the silicon layer. The silicon layer has multiple layers with different dopants and grain boundaries, which increases the overall resistance and reduces variations in conductivity between layers. This improves the reliability of devices containing the silicon layer.
Problems solved by technology
However, when the amount of the implanted dopants becomes less, variations of the conductivity between silicon layers become larger.
Since these silicon layers are fabricated with the same implantation process, but on different wafers, the reliability of devices containing these silicon layers is poor.
Method used
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[0013] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
[0014]FIGS. 1A through 1D are schematic cross-sectional views showing the steps of fabricating a silicon layer with high resistance according to a preferred embodiment of this invention. As shown in FIG. 1A, a silicon material layer 102 is formed on a substrate 100, wherein, the substrate 100 is formed with, for example, a dielectric layer 104 thereon, and a portion of the silicon material layer 102 is at least located on the dielectric layer 104. The dielectric layer 104 may be a gate dielectric layer, a shallow trench isolation (STI) or a field oxide isolation. In this embodiment, the silicon material layer 102 is located on the gate dielectric layer, for example. In addition, the silicon materia...
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Abstract
A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers and the interface layer have dopants therein. The amount of implanted dopants is about 1*1014˜5*1015 ions / cm2, and the silicon material layers have different grain boundaries.
Description
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of an application Ser. No. 11 / 160,046, filed on Jun. 7, 2005, now pending. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a silicon layer with high resistance and a fabricating method thereof. [0004] 2. Description of The Related Art [0005] In an integrated circuit process, a silicon layer plays an important role, especially in an application to a gate of a metal oxide semiconductor (MOS) or an interconnect structure. Generally speaking, the fabrication method of a silicon layer is to perform a chemical vapor deposition (CVD) process to form a silicon material layer, followed by performing an ion implantation process to implant dopants therein for increasing conductivity of the silicon material layer. [0006] I...
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IPC IPC(8): H01L21/20
CPCH01L29/4925H01L21/0245H01L21/28035H01L21/02532
Inventor YANG, YU-CHI
Owner UNITED MICROELECTRONICS CORP