Multi-component electronic package with planarized embedded-components substrate
a technology of embedded components and electronic packages, applied in the direction of electrical apparatus contruction details, semiconductor/solid-state device details, manufacturing tools, etc., can solve the problems of compromising package performance, fragile final package form, and inability to use silicon substrates in single-sided applications, etc., to achieve low profile, improve electrical performance of the package, and small footprint
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[0010]With reference to FIGS. 1A and 1B, a wafer 10 forms a substrate 12 for one or more IC chip packages. When cut into sections, e.g., 141, 142, 143, 144, each of those sections of the wafer 10 will define a separate package. The substrate 12 is typically composed of a dielectric material, such ceramics, glass, or plastics (e.g., epoxy, polyimide, or fluoropolymers). The substrate 12 has open cavities 16 into which IC die and other discrete electronic components will be placed. The width and length dimensions of the open cavities 16 are normally slightly larger than the components that will be inserted to allow tolerance for variations in the individual component size and room for adding an adhesive compound between the components and the inner periphery of the cavities 16.
[0011]Conductive vias 18 through the substrate 12 provide electrical pathways between the designated front and back surfaces 22F and 22B of the substrate 12 upon which electrical interconnects and other circuit ...
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