Method of Chemical Mechanical Polishing

Abstract

[Problem] To improve polishing efficiency while lowering shear force added to semiconductor wafers while increasing polishing speed, without damaging the wafer's processing surface or the membrane under it. [Solution Method] Pressing the revolving head or carrier 34 that holds fixed the semiconductor wafer 10 to the polishing pad or polishing cloth 30 attached to rotating polishing table 32 in this CMP device and while rotating carrier 34 and polishing table 32 respectively, and supplying liquid slurry to polishing pad 30 from nozzle 36, planarization by chemical processes and mechanical processes is carried out by removing membranes of the lower face of semiconductor wafer 10 (the processing surface). The chemical mechanical polishing process of the present invention in regard to the size of the relationship between the rotation rate of semiconductor wafer 10 fW and the number of rotations of polishing pad 30 fP has 3 fp<fW as its lower limit and 4 fp<fW<8 fp is ideal conditions.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates to a method of polishing the processed surface of a semiconductor wafer by mechanical polishing using the mutually rotary motion of the semiconductor wafer and the polishing pad and a chemical reaction. The present invention particularly relates to a superior method of chemical mechanical polishing (CMP) using a damascene process to shape the copper wiring embedded in an interlayer dielectric comprising a low-k organic membrane.FIELD OF THE INVENTION[0002]Today's integrated circuits, particularly large scale integrated circuits (LSI), possess multilayer wiring structures comprising multiple stacked circuit layers to increase the degree of miniaturization and integration. The process of forming the wiring of the prior art in multilayer wiring structures is that of forming a metal wire pattern by lithography or dry etching of aluminum and the like accumulated on the dielectric membrane. However, the fact that the electromi...

AI Technical Summary

Benefits of technology

[0014]In damascene processing, given that the polishing material copper is a relatively soft metal, and because the Young ratio of fluorocarbon membranes (organic low-k membranes) forming the interlayer insulation membrane is low, addition of a large shear stress due to the friction between the semiconductor wafer surface 10 and the polishing pad 30, will more easily result in damage such as the aforementioned peeling of the fluorocarbon insulation membrane or scratches to the copper and the like.

[0015]The present invention solves the aforementioned problems of the prior art and possesses the objective of providing a chemical mechanical polishing method that increases polishing performance without damaging the material of the wafer being polished or the lower membranes by lowering the shear stress added to the semiconductor while increasing the polishing speed.

Problems solved by technology

If this kind of membrane peeling or scratch occurs on a damascene interlayer insulation membrane and or embedded wires, the transmission characteristics of high frequency electrical current that flows along the surface of the wires (signal) or wire electrical properties are very greatly influenced and in some cases the LSI in question becomes defective.

In damascene processing, given that the polishing material copper is a relatively soft metal, and because the Young ratio of fluorocarbon membranes (organic low-k membranes) forming the interlayer insulation membrane is low, addition of a large shear stress due to the friction between the semiconductor wafer surface 10 and the polishing pad 30, will more easily result in damage such as the aforementioned peeling of the fluorocarbon insulation membrane or scratches to the copper and the like.

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