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Interconnect structure and method for forming the same

a technology of interconnection structure and integrated circuit, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, coatings, etc., can solve the problems of increasing interfering with the performance improvement of the semiconductor integrated circuit, and increasing the wiring delay. , to achieve the effect of further reducing the relative dielectric constant of the first insulating film

Inactive Publication Date: 2005-07-05
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

"The present invention provides an interconnection structure and a method for forming the same, which includes an interlevel insulating film made of organic-containing silicon di oxide with a low dielectric constant that can adhere strongly to metal interconnects, and a method for forming the same. The interconnection structure can be used in a semiconductor integrated circuit to increase the number of devices that can be integrated within a single semiconductor integrated circuit without modifying the conventional semiconductor device manufacturing process. The interlevel insulating film has a relative dielectric constant as low as that of an HSQ film, and can adhere to the metal interconnects. The method for forming the interconnection structure includes forming an interval insulating film using a reactive gas containing phenyltrimethoxy silane, forming wiring grooves and contact holes in the insulating film, and filling in the wiring grooves and contact holes with a metal film to interconnect the metal interconnects. The interconnection structure can reduce the relative dielectric constant of the interlevel insulating film and improve the adhesion between the insulating film and the metal interconnects."

Problems solved by technology

As the number of devices, integrated within a single semiconductor integrated circuit, has been tremendously increasing these days, wiring delay has also increasing noticeably.
This is because the larger number of devices integrated, the larger line-to-line capacitance (i.e., parasitic capacitance between metal interconnects), thus interfering with the performance improvement of a semiconductor integrated circuit.
However, the number of devices, integrated within a single semiconductor integrated circuit, will certainly continue to increase by leaps and bounds from now on, thus further increasing the wiring delay considerably.
Therefore, it is concerned that even the use of copper as an alternate metal interconnection material would not be able to catch up with such drastic increase.
Thus, it would be difficult to apply a silicon di oxide film to a semiconductor integrated circuit incorporating an even larger number of devices.
Nevertheless, a fluorine-doped silicon di oxide film is highly hygroscopic, and easily absorbs water in the air, resulting in various problems in practice, For example, when the fluorine-doped silicon di oxide film absorbs water, SiOH groups, having a high relative dielectric constant, are introduced into the film.
As a result, the relative dielectric constant of the fluorine-doped silicon di oxide film adversely increases, or the SiOH groups react with the water during a heat treatment to release H2O gas.
However, the HSQ film releases a larger amount of water than a conventional silicon di oxide film.
Accordingly, a usual resist application process is not applicable in such a situation, because the organic polymer film is likely to be damaged during ashing and removing the resist pattern.
As a result, the relative dielectric constant of the organic polymer film disadvantageously increases.
However, since the TiN film has a high resistance, the effective cross-sectional area of the metal interconnects decreases.
Consequently, the intended effect attainable by the use of the copper lines, i.e., reduction in resistance, would be lost.

Method used

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  • Interconnect structure and method for forming the same

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embodiment 1

[0057]Hereinafter, interconnection structure and method for forming the same according to the first embodiment of the present invention will be described with reference to FIGS. 1(a) through 1(c), FIGS. 2(a) through 2(c) and FIGS. 3(a) through 3(c).

[0058]First, as shown in FIG. 1(a), a first silicon nitride film 102 is formed over first metal interconnects 101 formed on a semiconductor substrate 100. The first silicon nitride film 102 is formed to be 50 nm thick, for example, and to protect the first metal interconnects 101 during a subsequent etching process step. Thereafter, a first organic-containing silicon di oxide film 103, containing an organic component in silicon di oxide, is formed to be 1 μm thick, for example, on the first silicon nitride film 102. Next, a second silicon nitride film 104 is formed to be 50 nm thick, for example, on the first organic-containing silicon di oxide film 103 and to protect the first organic-containing silicon di oxide film 103 during a subsequ...

embodiment 2

[0071]Next, interconnection structure and method for forming the same according to the second embodiment of the present invention will be described with reference to FIGS. 4(a) through 4(c), FIGS. 5(a) through 5(c) and FIGS. 6(a) through 6(c).

[0072]First, as shown in FIG. 4(a), a silicon nitride film 202 is formed over first metal interconnects 201 formed on a semiconductor substrate 200. The silicon nitride film 202 is formed to be 50 nm thick, for example, and to protect the first metal interconnects 201 during a subsequent etching process step. Thereafter, an organic-containing silicon di oxide film 203, containing an organic component in silicon di oxide, is formed to be 1 μm thick, for example, on the silicon nitride film 202. The organic-containing silicon di oxide film 203 may be deposited by any arbitrary technique. For example, the film 203 may be deposited by a CVD process using a reactive gas mainly composed of phenyltrimethoxy silane. In such a case, an organic-containin...

embodiment 3

[0102]Next, interconnection structure and method for forming the same according to the third embodiment of the present invention will be described with reference to FIGS. 12(a) through 12(c) and FIGS. 13(a) through 13(c).

[0103]First, a metal film is deposited on a semiconductor substrate 300 and then selectively dry-etched and patterned, thereby forming first metal interconnects 301. Then, a first organic-containing silicon di oxide film 302 (i.e., an exemplary first insulating film), containing an organic component in silicon di oxide, is deposited to be 20 mm thick, for example, and to cover the first metal interconnects 301 such that grooves are left between the first metal interconnects 301. The first organic-containing silicon di oxide film 302 may be deposited by any arbitrary technique. For example, the film 302 may be deposited by a CVD process using a reactive gas mainly composed of phenyltrimethoxy silane.

[0104]Next, a low-dielectric-constant insulating film 303 (i.e., an ...

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Abstract

An interconnection structure includes an interlevel insulating film, made of organic-containing silicon di oxide, between lower- and upper-level metal interconnects. A phenyl group, bonded to a silicon atom, is introduced into silicon di oxide in the organic-containing silicon di oxide.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates to interconnection structure and method for forming the same in a semiconductor integrated circuit.[0002]As the number of devices, integrated within a single semiconductor integrated circuit, has been tremendously increasing these days, wiring delay has also increasing noticeably. This is because the larger number of devices integrated, the larger line-to-line capacitance (i.e., parasitic capacitance between metal interconnects), thus interfering with the performance improvement of a semiconductor integrated circuit. The wiring delay is so-called “RC delay”, which is proportional to the product of the resistance of metal interconnection and the line-to-line capacitance.[0003]In other words, to reduce the wiring delay, either the resistance of metal interconnection or the line-to-line capacitance should be reduced.[0004]In order to reduce the interconnection resistance, IBM Corp., Motorola, Inc., etc. have reported semico...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/469H01L21/02H01L21/316H01L21/768H01L23/522
CPCH01L21/02126H01L21/02216H01L21/02271H01L21/76801H01L21/76807H01L21/76811H01L21/76834H01L21/76835H01L2924/0002H01L2924/00H01L21/31612H01L21/31633
Inventor AOI, NOBUO
Owner PANASONIC CORP