Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

Abstract

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I / O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I / O lines to which designated sub-common I / O lines are connected selectively.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This applicationMore than one reissue application has been filed for the reissue of U.S. Pat. No. 5,966,341. The reissue applications are application Ser. Nos. 11 / 176,881 (the present application); 09 / 974,962; 11 / 759,316 and 11 / 759,345. Ser. Nos. 11 / 759,316 and 11 / 759,345, were both filed on Jun. 7, 2007 and are continuations of the present application. The present application is a continuation of Ser. No. 09 / 974,962, filed on Oct. 12, 2001(now RE38944), which is a Reissue of U.S. Pat. No. 5,966,341, filed as Ser. No. 08 / 982,398 on Dec. 2, 1997, which <?insert-end id="INS-S-00001" ?>is a continuation of application Ser. No. 08 / 779,835, filed on Jan. 7, 1997, now U.S. Pat. No. 5,777,927, which is a continuation of application Ser. No. 08 / 574,104, filed Dec. 20, 1995 (now U.S. Pat. No. 5,604,697) the entire disclosures of which isare hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to a se...

AI Technical Summary

Benefits of technology

"The present invention provides a dynamic RAM that takes full advantage of the benefits of a layered structure to improve its operation speed, increase its circuit integration, and reduce its manufacturing cost. The invention involves a semiconductor memory that has a layered word line structure with a main word line and column selection signal lines intersecting orthogonally, and main common I / O lines to which designated sub-bit lines are connected selectively. The sub-bit lines are driven by sub-word line driving circuits, and the main word lines have a pitch that is an integer multiple of the pitch of the sub-bit lines. The sub-bit lines are connected to the main common I / O lines via column selection switches. The invention also includes a layer of sub-common I / O lines to which designated sub-bit lines are connected selectively. The sub-main amplifiers are pseudo-direct sense type sub-amplifiers located in the region where the sub-word line driver and the sense amplifier intersect. The invention provides a comprehensive layered structure involving all word lines, bit lines, and common I / O lines, which enhances the operation speed, circuit integration, and scale of the semiconductor memory."

Problems solved by technology

This poses constraints on the effort to improve the access time of dynamic RAMs in read mode.

Because the common I / O lines are not layered, the load on the sense amplifiers increases, which hampers the improvement of access time.

This necessitates narrowing the wiring pitch of the metal wiring layer constituting the word lines, which in turn restricts the effort to boost the degree of circuit integration of dynamic RAMs.

This poses constraints on the attempts to boost the degree of circuit integration of dynamic RAMs.

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