Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for processing porous membrane

A treatment method and porous membrane technology, which can be used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., and can solve problems such as the impact of semiconductor device performance

Inactive Publication Date: 2008-03-05
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

thereby negatively affecting the performance of semiconductor devices

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for processing porous membrane
  • Method for processing porous membrane

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0016] A silicide film with a thickness of 50 Å (Angstrom) to 1000 Å is deposited on the porous film after dual damascene patterning and etching by plasma treatment to seal the exposed pores of 8 nm to 25 nm.

[0017] The conditions for plasma treatment are:

[0018] The gas in the reaction chamber is SiH 4 / N 2 O / N 2 / He / O 2 / Ar,

[0019] The heating temperature of the substrate is 200°C to 400°C,

[0020] The applied radio frequency (RF) power is 50W to 200W.

[0021] Form a silicide film with a film thickness of 50 Ȧ (Angstrom) to 1000 Ȧ, for example, a silicon dioxide film (SiO 2 ), or SiON film, or SiN film.

[0022] Subsequently, on the formed silicide film, tantalum (Ta) / tantalum nitride (TAN) and copper (Cu) films constituting interconnect lines are sequentially formed.

[0023] If the cleaning process is performed after the dual damascene patterning and etching have been performed, if the cleaning process is performed by wet etching, the process of adding a si...

no. 2 example

[0025] A silicide film with a film thickness of 50 Å (Angstrom) to 1000 Å is deposited on the porous film after dual damascene patterning and etching by plasma treatment to seal the exposed pores with a diameter of 8 nm to 25 nm.

[0026] The conditions for plasma treatment are:

[0027] The gas in the reaction chamber is SiH 4 / N 2 O / N 2 / He / O 2 / Ar,

[0028] The heating temperature of the substrate is 200°C to 400°C,

[0029] The applied radio frequency (RF) power is 50W to 200W.

[0030] A silicide film, such as a silicon dioxide film (SiO 2 ), or SiON film, or SiN film.

[0031] Subsequently, on the formed silicide film, tantalum (Ta) / tantalum nitride (TAN) and copper (Cu) films constituting interconnect lines are sequentially formed.

[0032] This embodiment is basically the same as the first embodiment, except that the reaction gas in the reaction chamber uses SiN 4 Instead of SiH used in the first embodiment 4 .

[0033] If the cleaning process is performed a...

no. 3 example

[0035] A silicide film with a film thickness of 50 Å (Angstrom) to 1000 Å is deposited on the porous film after dual damascene patterning and etching by plasma treatment to seal the exposed pores with a diameter of 8 nm to 25 nm.

[0036] The conditions for plasma treatment are:

[0037] The gas in the reaction chamber is SiH 4 / N 2 O / N 2 / He / O 2 / Ar,

[0038] The heating temperature of the substrate is 200°C to 400°C,

[0039] The applied radio frequency (RF) power is 50W to 200W.

[0040] Form a silicide film with a film thickness of 50 Ȧ (Angstrom) to 1000 Ȧ, for example, a silicon dioxide film (SiO 2 ), or SiON film, or SiN film.

[0041] Subsequently, on the formed silicide film, tantalum (Ta) / tantalum nitride (TaN) and copper (Cu) films constituting interconnect lines are sequentially formed.

[0042] This embodiment is basically the same as the first embodiment, except that the reaction gas in the reaction chamber uses the SiH used in the first embodiment of OMC...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Processes of plasma or physical vapor deposition for dielectric layer are carried out on porous membrane, where double-inlaid composition and etching steps are completed. Silicide film in thickness 50 - 1000 angstrom is deposited in order to close down exposed holes with diameter from 8nm to 25nm. The deposited silicide film is silicon dioxide (SiO2) film or SiON film or SiN film.

Description

technical field [0001] A method for manufacturing a semiconductor device, particularly a method for treating a porous film. Background technique [0002] In the manufacturing process of semiconductor devices, various porous films, such as porous anodized films, etc. are to be formed (see Chinese Patent Grant No., CN-1038885C). After these porous films are patterned by photolithographic etching, the holes on the side walls of the formed patterns will be exposed, and these exposed holes are easy to absorb moisture and adsorb chemicals used in subsequent processes in the subsequent processes. Thus, the performance of the semiconductor device is negatively affected. Contents of the invention [0003] In order to overcome the defect that the exposed holes on the patterned sidewall of the porous film in the semiconductor device will absorb moisture and adsorb chemical substances in the subsequent process and negatively affect the performance of the semiconductor device after pa...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/00
Inventor 汪钉崇
Owner SEMICON MFG INT (SHANGHAI) CORP