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Radiation type packaging structure and its making method

A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of increasing the complexity and cost of the overall packaging process, affecting the appearance of packaged products, etc., to reduce packaging costs and Mold management costs, removal steps and cost savings, and the effects of simplified operations

Inactive Publication Date: 2008-11-12
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] However, in the actual operation of the above-mentioned semiconductor assembly process, the film 42 temporarily attached to the chip 40 before is easy to cause the adhesive material of the film 42 to remain on the packaging compound 44 when it is torn off, which not only affects the appearance of the packaged product, but also At the same time, additional cleaning operations are often required, which increases the complexity and cost of the overall packaging process

Method used

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  • Radiation type packaging structure and its making method
  • Radiation type packaging structure and its making method
  • Radiation type packaging structure and its making method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] Please refer to FIG. 5A to FIG. 5H , which are schematic diagrams of the manufacturing process of Embodiment 1 of the manufacturing method of the heat-dissipating package structure of the present invention.

[0055] As shown in FIG. 5A , firstly, a matrix substrate module sheet 50A is provided, and the substrate module sheet 50A is formed by arranging a plurality of substrate units 50 in a matrix. Each substrate unit 50 has an upper surface 500 and a lower surface 501 respectively, and is provided with a through hole 502 . It should be noted that the substrate units 50 can also be arranged in a linear manner in addition to being arranged in a matrix, and a single substrate unit can also be used if the process conditions permit.

[0056] As shown in Figure 5B, on the upper surface 500 of each substrate unit 50, the active surface 51a of the chip 51 is placed on it at a predetermined position through an adhesive layer 55 such as silver glue, and the chip 51 is closed to t...

Embodiment 2

[0067] Figure 7A to Figure 7G It is a schematic diagram of the manufacturing process of Embodiment 2 of the manufacturing method of the heat dissipation package structure of the present invention. The process of the second embodiment of the present invention is substantially the same as that of the first embodiment, the main difference is that the semiconductor chip in the second embodiment is flip-chip connected and electrically connected to the substrate.

[0068] As shown in FIG. 7A , firstly, a matrix substrate module sheet 70A is provided, and the substrate module sheet 70A is composed of a plurality of substrate units 70 arranged in a matrix. Each of the substrate units 70 has an upper surface 700 and a lower surface 701 . It should be noted that the substrate units 70 can also be arranged in a linear manner in addition to being arranged in a matrix, and a single substrate unit can also be used if the process conditions permit.

[0069] As shown in FIG. 7B , at a prede...

Embodiment 3

[0080] Figure 9AIt is a schematic cross-sectional view of Example 3 of the semiconductor package structure manufactured with reference to the method for manufacturing the heat-dissipating package structure of the present invention. The semiconductor package structure of the present invention is made by a method similar to that of the semiconductor structures of Example 1 and Example 2. The difference is that the semiconductor package structure of Example 3 uses a QFN lead frame 90 as the semiconductor chip 91 chip carrier, the semiconductor chip 91 is flip-chip connected and electrically connected to the pin 90a of the QFN lead frame, for subsequent electrical connection to an external device via the pin 90a, and on the chip 91 A heat sink 93 with a hollow structure 930 can be placed on the passive surface 91b of the chip 91 by, for example, a thermally conductive adhesive layer 95. The size of the chip 91 is larger than the size of the hollow structure 930, so that the passi...

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Abstract

The invention relates to a heat loss type sealed structure and it's making method. The structure comprises a chip carrier, a semiconductor chip electric connected with the chip carrier, a hest loss sheet with a first surface and a second surface to form the hollow out structure, wherein the second surface of the heat loss sheet is connected with the chip; the chip size is above the hollow out structure size so that the chip can expose partly of the hollow out structure; the sealed colloid formed between the heat loss sheet and the chip carrier to coat the chip cam make the first surface of the heat loss sheet and the frank surface of the fist surface expose the atmosphere; the chip is electric connected with the external part by a plurality of conducing units on the chip carrier provide.

Description

technical field [0001] The invention relates to a semiconductor package and its manufacturing method, in particular to a ball grid array (BGA) packaging structure with heat sink and its manufacturing method. Background technique [0002] Ball Grid Array (BGA) is an advanced semiconductor chip packaging technology, which is characterized in that a semiconductor chip is placed on a substrate, and a plurality of solder balls (Solder Ball) arranged in a grid are implanted on the back of the substrate. , so that more input / output connection terminals (I / O Connection) can be accommodated on the semiconductor chip carrier of the same unit area to meet the needs of highly integrated semiconductor chips, and the entire packaging unit is connected by these solder balls Solder and electrically connect to an external printed circuit board. [0003] When a highly integrated semiconductor chip is running, it will be accompanied by a large amount of heat generation. Since the encapsulatio...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L23/12H01L23/48H01L23/34
CPCH01L24/97H01L2224/16225H01L2224/16245H01L2224/32225H01L2224/32245H01L2224/48091H01L2224/4824H01L2224/48247H01L2224/73215H01L2224/73265H01L2224/97H01L2924/15311H01L2924/351H01L2924/00014H01L2924/00
Inventor 黄建屏萧承旭
Owner SILICONWARE PRECISION IND CO LTD