A prodcution method for nano coulomb structure

A nano-scale, tunnel junction technology is applied in the field of preparation of nano-scale Coulomb island structures, which can solve the problems of poor reliability, high preparation cost, complicated preparation process, etc., and achieve the effects of increasing working temperature, reducing preparation cost and improving preparation efficiency.
CN100466204CInactive Publication Date: 2009-03-04INST OF MICROELECTRONICS CHINESE ACAD OF SCI

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2009-03-04
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a preparing method of nanometer-class coulomb island structure, it includes: A. smearing electron slushing compound on conducting layer of underlay; B. baking the electron slushing compound; C. electron beam exposing the electron slushing compound; D. imaging the electron slushing compound exposed; E. fixing the electron slushing compound imaged; F. process of glue-eliminating and high temperature oxidation is proceeded to coulomb island structure obtained to obtain nanometer-class coulomb island structure whose size is more smaller. With the invention, preparing craftwork is simplified, cost is decreased, efficiency is increased, and reliability of coulomb island structure is increased. The preparing method provided in the invention possesses advantages that it is compatible with traditional CMOS, fits for the extending and application.
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Description

technical field

[0001] The invention relates to the technical field of nano-electronic devices and nano-processing, in particular to a method for preparing a nano-scale Coulomb island structure for making single-electron devices. Background technique

[0002] Integrated circuits with complementary metal oxide semiconductor (CMOS) devices as the mainstream technology have been following Moore's law and developed rapidly. In 2004, integrated circuits entered the 90nm technology node. As the feature size enters the nanoscale, the traditional CMOS technology is facing more and more serious challenges. Therefore, nanoelectronic devices based on new principles have become a research hotspot.

[0003] Single-electronic devices have the advantages of small size, fast speed, low power consumption, and large-scale integration, and have very broad application prospects, such as making single-electronic memory, single-electronic logic circuits, current standards, ultra-sensitive electro...

Claims

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