Grid and semiconductor device manufacture method, structure for manufacturing grid
A manufacturing method and semiconductor technology, which are applied to the manufacturing of gates and semiconductor devices, and the structure of gates, can solve the problems of poor gate 104a profile, affecting gate switching characteristics, and large sidewall roughness, etc. Small roughness, improved opening sensitivity, and the effect of protecting sidewalls
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[0053] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0054] Figure 7 to Figure 17 It is a schematic cross-sectional view of the structure corresponding to each step of the embodiment of the gate manufacturing method of the present invention.
[0055] Such as Figure 7 As shown, a semiconductor substrate 10 is provided, and the material of the semiconductor substrate 10 can be one of single crystal silicon, polycrystalline silicon, and amorphous silicon, and the material of the semiconductor substrate 10 can also be a silicon germanium compound. The semiconductor substrate 10 may also have a silicon-on-insulator (SOI) structure or an epitaxial layer structure on silicon (not shown). N-type impurities or P-type impurities can be doped into the semiconductor substrate 10 to form N wells or P wells.
[0056] A gate dielectric layer 11 is formed on the semiconductor substrate 10 . The gate d...
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