Grid and semiconductor device manufacture method, structure for manufacturing grid

A manufacturing method and semiconductor technology, which are applied to the manufacturing of gates and semiconductor devices, and the structure of gates, can solve the problems of poor gate 104a profile, affecting gate switching characteristics, and large sidewall roughness, etc. Small roughness, improved opening sensitivity, and the effect of protecting sidewalls

Active Publication Date: 2009-11-18
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0011] However, in the above method, due to the multi-step etching, the profile of the sidewall layer 108a as a hard mask layer is poor, which in turn leads to poor profile of the formed gate 104a and large sidewall roughness, which affects The switching characteristics of the formed gate

Method used

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  • Grid and semiconductor device manufacture method, structure for manufacturing grid
  • Grid and semiconductor device manufacture method, structure for manufacturing grid
  • Grid and semiconductor device manufacture method, structure for manufacturing grid

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Embodiment Construction

[0053] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0054] Figure 7 to Figure 17 It is a schematic cross-sectional view of the structure corresponding to each step of the embodiment of the gate manufacturing method of the present invention.

[0055] Such as Figure 7 As shown, a semiconductor substrate 10 is provided, and the material of the semiconductor substrate 10 can be one of single crystal silicon, polycrystalline silicon, and amorphous silicon, and the material of the semiconductor substrate 10 can also be a silicon germanium compound. The semiconductor substrate 10 may also have a silicon-on-insulator (SOI) structure or an epitaxial layer structure on silicon (not shown). N-type impurities or P-type impurities can be doped into the semiconductor substrate 10 to form N wells or P wells.

[0056] A gate dielectric layer 11 is formed on the semiconductor substrate 10 . The gate d...

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Abstract

A gate manufacturing method, comprising: providing a semiconductor substrate having a gate layer; forming a first material layer on the gate layer; forming a second material layer on the first material layer; patterning the first material layer Two material layers, forming a second material layer pattern; forming a sidewall layer on the sidewall of the second material layer pattern; removing the second material layer pattern; etching the first material layer not covered by the sidewall layer and gate layer to form a gate. The invention also provides a manufacturing method of a semiconductor device and a structure for forming a gate. The gate profile formed by this method is better.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a grid, a semiconductor device, and a structure for manufacturing the grid. Background technique [0002] With the development of semiconductor technology in the direction of small line width and high integration, the line width of the gate representing the semiconductor manufacturing process level is getting smaller and smaller, which puts forward higher requirements for the photolithography process, and the optical exposure wavelength is also developed from 365nm To 248nm, 193nm or even smaller, the immersion exposure technology based on high refractive index medium has also been developed. [0003] However, due to the continuous shrinking of the grid size, the size of the pattern on the photolithography mask is getting smaller and smaller, and the pitch of the pattern is getting closer and closer. Limited by the lithography resolu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/308H01L29/423
Inventor 朱峰张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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