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Checking method and element manufacture method

A device manufacturing method and inspection method technology, which is applied in semiconductor/solid-state device manufacturing, instruments, electrical components, etc., can solve problems such as poor repeatability, not necessarily accurately reflecting the processing status of the projection system chip or target, and low sensitivity

Inactive Publication Date: 2009-12-09
ASML NETHERLANDS BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These techniques, also offline techniques, have the disadvantage that they all use local measurements that do not necessarily accurately reflect the projection system or the processing status on all patches or targets
However, the reconstruction of the structure must be computationally very deep, and this technique may suffer from low sensitivity and poor repeatability

Method used

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  • Checking method and element manufacture method
  • Checking method and element manufacture method
  • Checking method and element manufacture method

Examples

Experimental program
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Effect test

Embodiment 1

[0066] According to a first method of the invention, which is used to measure overlay, the test structure printed on the substrate W comprises a first mark or first pattern component G1 printed on the upper handle layer TL, and a first mark or pattern component G1 printed on the lower handle layer BL. The second mark or second pattern component G2 on. Masks G1 and G2 may take any convenient form, such as raster, checker pattern, box, frame, herringbone and the like. The form of marking is chosen for ease of reconstruction, especially the use of rasters allows the use of fast reconstruction techniques. The type of labeling can also be selected for improved sensitivity. If printed accurately, and not affected by subsequent processing, the two marks G1 and G2 should be identical, with no overlay errors, and perfectly aligned. Although the first and second marks (pattern components) are identical in form, their positions on the substrate treatment layer are different. When the ...

Embodiment 2

[0070] The grating structure used in the second method of the present invention is drawn in Figure 8 to Figure 10 middle. The second method of the invention measures differential dimensional asymmetries caused by coma aberrations in the lithographic apparatus, in particular the projection system PL, or by processes acting on the substrate.

[0071] like Figure 8 As shown, the test pattern G includes an inner pitch P i and outer spacing P o double bar grating. The first pattern component includes a single grating whose pitch is equal to the inner pitch, and the second pattern component includes a single grating whose pitch is equal to the outer pitch. Two reference gratings RG1', RG2' such as Figure 9 and Figure 10 shown, respectively, including spacing for P i A single grating and P o single raster.

[0072] As in the first method, the test pattern G and the reference patterns RG1', RG2' are also irradiated with reflected polarized light. The resulting reflection...

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Abstract

To enhance scatterometry consisting of two-component test patterns, reference patterns corresponding to each component of the two-component pattern are also printed. The scatterometry signal is acquired from the reference pattern, corresponds to the individual components of the test pattern, and is used to enhance the signal from the test pattern, thereby improving sensitivity and signal-to-noise ratio.

Description

technical field [0001] The present invention relates to inspection methods that can be used for device fabrication by photolithographic techniques, and methods for fabricating devices using photolithographic techniques. Background technique [0002] A lithographic apparatus is a machine that applies a desired pattern to a target portion of a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that case, a patterning device, such as a mask, can be used to form a circuit pattern corresponding to an IC monolayer, which can be imaged on a substrate (such as a silicon wafer) with a layer of radiation-sensitive material (resist) On a target portion (eg, a portion comprising one or many small pieces). Typically, a single substrate consists of a grid of adjacent target portions exposed in succession. Known lithographic apparatuses comprise so-called steppers, in which each target portion is irradiated by exposing the e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20G03F1/08G03F9/00H01L21/027
CPCG03F7/706G03F7/70633H01L21/027
Inventor M·杜萨A·J·登博夫
Owner ASML NETHERLANDS BV
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