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Process for etching openings in dielectric layer

A dielectric layer, etching technology, used in circuits, electrical components, semiconductor/solid-state device manufacturing, etc.

Inactive Publication Date: 2007-09-19
LAM RES CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Photoresist / hardmask facets can cause channels / trenches to "overshoot" device critical dimensions, while low selectivity to etch stop layer can cause significant sputtering onto via sidewalls

Method used

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  • Process for etching openings in dielectric layer
  • Process for etching openings in dielectric layer
  • Process for etching openings in dielectric layer

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Embodiment Construction

[0025] The present invention provides a method of semiconductor fabrication for the manufacture of integrated circuits in which a plurality of openings can be plasma etched in a dielectric layer, such as an oxide layer, while providing an overlying photoresist and / or hard mask layer Provide desired selectivity and material integrity. Furthermore, the present invention can improve the profile of etched contacts in device fabrication. The method of the invention can be used to etch various dielectric layers, e.g., undoped silicon oxide and doped silicon oxide, e.g., fluorinated silicon oxide (FSG), spin-on-glass (SOG); silicate glasses, e.g., Phosphate borosilicate glass (BPSG), phosphate silicate glass (PSG), organosilicate glass (OSG), and carbon-doped silicate glass (e.g., CORAL, commercially available from Novellus Systems, Inc. products); doped or undoped thermally grown silicon oxide; doped or undoped TEOS deposited silicon oxide; aromatic hydrocarbon polymers, for exampl...

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PUM

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Abstract

A process of etching openings in a dielectric layer includes supporting a semiconductor substrate in a plasma etch reactor, the substrate having a dielectric layer and a patterned photoresist and / or hardmask layer above the dielectric layer; supplying to the plasma etch reactor an etchant gas comprising (a) a fluorocarbon gas (CxFyHz, where x>=1, y>=1, and z>=0), (b) a silane-containing gas, hydrogen or a hydrocarbon gas (CxHy, where x>=1 and y>=4), (c) an optional oxygen-containing gas, and (d) an optional inert gas, wherein the flow rate ratio of the silane-containing gas to fluorocarbon gas is less than or equal to 0.1, or the flow rate ratio of the hydrogen or hydrocarbon gas to fluorocarbon gas is less than or equal to 0.5; energizing the etchant gas into a plasma; and plasma etching openings in the dielectric layer with enhanced photoresist / hardmask to dielectric layer selectivity and / or minimal photoresist distortion or striation.

Description

technical field [0001] The present invention relates to an improved method for plasma etching a dielectric layer in the manufacture of integrated circuits. In particular, the present invention relates to enhanced photoresist and / or hardmask facet selectivity to maintain critical dimension (CD), minimize streaking, and improve profile when etching dielectric layers. Background technique [0002] A common requirement in the manufacture of integrated circuits is the plasma etching of openings such as contacts, vias and trenches in dielectric materials. These dielectric materials include doped silicon oxide (eg, fluorinated silicon oxide), undoped silicon oxide, silicate glass (eg, borosilicate phosphate glass (BPSG) and phosphate silicate glass ( PSG)), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, organic and inorganic low-k materials, etc. The dielectric dopants include boron, phosphorus and / or arsenic. [0003] The dielectr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/311H01L21/768H01L21/3065H01L21/027H01L21/3213
CPCH01L21/0276H01L21/32139H01L21/31138H01L21/32136H01L21/31116
Inventor 阿龙·埃普勒穆昆德·斯里尼瓦桑罗伯特·舍比
Owner LAM RES CORP