Self-adaptable package for designing on-chip network

Abstract

The method feature the following: setting up a data source buffer area at IP block; setting up a packager and a packaging buffer area at the network interface; after system initiation, the packager is at a idle state; when the data source buffer area is not empty and the packaging buffer area is not full, the packager inserts header and tailor and body micro plate, and enters into the busy state; if the data source buffer area is not empty and the packaging buffer area is not full, and the destination address of the data is not changed, the packager inserts the body micro plate; if the destination address in the data buffer source area is changed or the data source buffered area and the packaging buffer area both are empty, the packager inserts the body micro plate and enters into idle state.

Description

technical field [0001] The invention belongs to the field of on-chip interconnection network design. Background technique [0002] Integrated circuits have been advancing in accordance with Moore's Law. The number of TP (Intellectual Property) blocks integrated in a single chip is increasing. The traditional bus-based on-chip interconnection structure has already performed better in terms of bandwidth, power consumption, reliability, and scalability. Increasingly, on-chip communication has replaced computation as the bottleneck in IC design. Network-on-Chip (NoC), as a key technology in the field of integrated circuit design, is used to solve the problem of on-chip interconnection caused by the increase in chip size. [0003] Packet switching is widely used in the design of network-on-chip because of its advantages such as high link utilization. Wormhole routing is also unanimously recommended by network-on-chip researchers because of its advantages in area and delay. In ...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to propose a self-adaptive packaging method for network on chip design, to overcome the shortcomings of wasting network capacity and increasing power consumption of network on chip in the current fixed-length packaging method

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