Low disturbance single grid non-volatile memory and operation approach thereof
A non-volatile, method of operation technology, applied in static memory, read-only memory, information storage, etc., can solve the problems of increasing the cost of boosting area, consuming large current, increasing production cost, etc. effect of speed improvement
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Embodiment 5
[0143] In addition, the present invention also provides a fifth embodiment, which uses a negative voltage applied to the P-type well, so that the absolute voltage of the drain or gate becomes smaller (less than 5V) during programming and erasing, so as to achieve low voltage and low current consumption operating effect.
[0144] FIG. 9 is a cross-sectional view of a single-gate nonvolatile memory structure provided by Embodiment 5 of the present invention.
[0145] The low-interference single-gate non-volatile memory structure 500 includes an NMOS transistor 510 and an N-type capacitor structure 520 in a P-type well 517, wherein a second ion is formed under the dielectric layer of the N-type capacitor structure 520. The doped region buried layer 524, the second ion-doped region buried layer 524 is adjacent to the P-type well 517, and the above-mentioned P-type well 517 is arranged on the N-type semiconductor substrate 530; and the first conductive gate of the NMOS transistor 5...
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