Copper interconnected fabricating method for semiconductor device and structure thereof

Abstract

This invention relates to a manufacturing method for semiconductor apparatuses connected by copper including providing a semiconductor substrate with a medium isolation layer and a copper layout layer inserted in the medium isolation layer, forming a diffusion blocking layer on the surface of the copper layout layer and the isolation layer, and the diffusion blocking layer is a TaN material in a face-centered cubic structure with an Al cushion layer formed on it. This invention also provides a structure based on this method, which changes the technology and structure of a deposited diffusion blocking layer by turning the crystal structure of TaN film from body-centered cubic structure to a face-centered cubic structure to be covered on the Cu layout layer.

Description

technical field [0001] The invention relates to a manufacturing method and structure of a semiconductor device, in particular to a manufacturing method and structure of a copper interconnected semiconductor device. Background technique [0002] With the continuous improvement of the integration level of integrated circuits, the performance of Al as an interconnection material has been difficult to meet the requirements of integrated circuits. Cu has lower resistivity and higher electromigration resistance than Al, and has been widely used in deep submicron technology. However, Cu is the culprit leading to device failure, mainly because Cu is a heavy metal that can rapidly diffuse in semiconductor silicon wafers and silicon dioxide under high temperature and electric field, causing problems in device reliability. Therefore, between the Cu wiring layer and the dielectric isolation layer, a diffusion barrier layer material that prevents Cu diffusion must be added, such as TaN,...

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Problems solved by technology

[0009] The electromigration (EM) characteristics of 15 units from S31 to S45 on the same wafer were tested to analyze the failure of the device. The results are shown in Figure 4. It can be seen that unit S31 formed a resistance peak as early as 2 hours, and the rest The cells showed a resistance peak before 10 hours, indicating that these cells had voids within 10 hours of testing, causing device failure

[0010] From the above discussion, it can be seen that the TaN diffusion barrier layer with body-centered cubic structure has weak ability to prevent Cu diffusion and electromigration.

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