Non-volatile memory and its manufacturing method

Abstract

The invention discloses a nonvolatile memory, which includes a basement, an active layer, an element isolation layer and a memory cell. The active layer is arranged on the basement and protrudes from the surface of the basement. A plurality of element isolation layers are arranged on both sides of the active layer, and the surface of the element isolation layer is lower than the surface of the active layer. The memory cell comprises a control grid, a charge storage layer, a roof cover layer and a source electrode / drain electrode region. The control grid is arranged on the basement across the active layer. The charge storage layer is arranged on the lateral wall of the active layer and is located between the control grid and the active layer. The roof cover layer is arranged on the top of the active layer and is located between the control grid and the active layer. The source electrode / drain electrode region is arranged in the active layer at the both sides of the control grid.

Description

technical field [0001] The present invention relates to a semiconductor element, and in particular to a nonvolatile memory and a manufacturing method thereof. Background technique [0002] Among all kinds of memory products, non-volatile memory, which has the advantage of being able to store, read or erase data multiple times, and the stored data will not disappear after power off, has become a personal A memory element widely used in computers and electronic equipment. [0003] A typical EEPROM uses doped polysilicon to make a floating gate and a control gate. However, when there are defects in the tunnel oxide layer under the doped polysilicon floating gate layer, it is easy to cause leakage current of the device, which affects the reliability of the device. [0004] Therefore, in the known technology, a charge trapping layer is also used to replace the polysilicon floating gate, and the material of the charge trapping layer is, for example, silicon nitride. The silicon...

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Problems solved by technology

[0006] However, the program of writing and reading the memory cells in the NAND array is more complicated, and because many memory cells are connected in series in the array, the read current of the memory cells is small, and the The problem that causes the operation speed of the memory cell to slow down and cannot improve the performance of the device

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