Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method of manufacturing semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as increased resistance and inability of field-effect transistors to work at high speeds, and achieve the effect of improving reliability and performance

Active Publication Date: 2011-09-21
RENESAS ELECTRONICS CORP
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the development of high integration of semiconductor devices, field effect transistors (MISFET: Metal Insulator Semiconductor Field Effect Transistor) are miniaturized according to the scaling rule, but the gate or source The resistance of the electrode and the drain increases, and there is a problem that even if the field effect transistor is miniaturized, it cannot operate at high speed

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method of manufacturing semiconductor device
  • Method of manufacturing semiconductor device
  • Method of manufacturing semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0152] Next, the semiconductor device manufacturing process of this embodiment will be described with reference to the drawings. Figure 1 to Figure 8 It is a sectional view of main parts in the manufacturing process of a semiconductor device which is one embodiment of the present invention, for example, a semiconductor device having a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor).

[0153] First, if figure 1 As shown, a p-type semiconductor substrate (semiconductor wafer) 1 made of single crystal silicon or the like having a resistivity of, for example, about 1 to 10 Ωcm is prepared. Then, the semiconductor substrate 1 is thermally oxidized to form an insulating film 2 with a thickness of about 11 nm, for example, on the surface thereof, and then deposited on the upper layer of the insulating film with a thickness of about 90 nm by CVD (Chemical Vapor Deposition) or the like. The insulating film 3. The insulating film 2 is made of silicon oxi...

Embodiment approach 2

[0322] Figure 31 is a manufacturing process flowchart showing a part of the semiconductor device manufacturing process of this embodiment, and corresponds to the above-mentioned first embodiment. Figure 9 . Figure 31 means to get the above Figure 7 After the structure of the gate electrode 8a, 8b, n + type semiconductor region 9b and p + The manufacturing process flow of the step of forming a metal silicide layer (metal-semiconductor reaction layer) on the surface of the type semiconductor region 10b. Figure 32 ~ Figure 35 It is a sectional view of main parts in the manufacturing process of the semiconductor device of this embodiment.

[0323] In the manufacturing process of the semiconductor device of this embodiment, the steps up to the removal of the isolation film 13 and the unreacted metal film 12 by wet cleaning in the above-mentioned step S4 are the same as the above-mentioned embodiment 1, so the description is omitted here, and the above-mentioned step S4 Th...

Embodiment approach 3

[0339] The inventors of the above Figure 18 ~ Figure 21 After further research on the process of the comparative example, it was found that compared with the n-channel MISFET, the source and drain of the p-channel MISFET are prone to increase in junction leakage current and uneven junction leakage due to the formation of the nickel silicide layer 141b. (variation of junction leakage current for each transistor).

[0340] In order to reduce the above-mentioned junction leakage current, it is effective to reduce the thickness of the Ni film 112 deposited on the semiconductor substrate 1, thereby reducing the thickness of the nickel silicide layer 141b. However, the nickel silicide layer 141b is provided for low resistance. Therefore, if the thickness of the nickel silicide layer 141b of both the n-channel type MISFET and the p-channel type MISFET is reduced, even the n-channel type MISFET that is less likely to affect the junction leakage current will cause the nickel silicide...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention improves performance of a semiconductor device having a metal silicide layer by using a salicide process. After forming gate insulation films 7, gate electrodes 8a and 8b, and n<+> type semiconductor regions 9b and p<+> type semiconductor regions 10b for sources and drains are formed, a metal film and a barrier film are formed on a semiconductor substrate 1, and the metal film, the gate electrodes 8a and 8b, the n<+> type semiconductor regions 9b and the p<+> type semiconductor regions 10b are reacted with one another by executing a first heat treatment, whereby a metal silicide layer 41 formed of mono-silicide MSi of a metal element M constituting the metal film is formed. Thereafter, the barrier film and the unreacted metal film are removed, and thereafter the metal silicide layer 41 is stabilized by executing a second heat treatment. Hereafter, a treatment setting the temperature of the semiconductor substrate 1 higher than the heat treatment temperature of the second heat treatment is not executed. The heat treatment temperature of the second heat treatment is set lower than a temperature at which the lattice size of the disilicide MSi2 of the metal element M coincides with that of the semiconductor substrate 1.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a technique effectively applicable to the manufacture of a semiconductor element having a metal silicide layer. Background technique [0002] With the development of high integration of semiconductor devices, field effect transistors (MISFET: Metal Insulator Semiconductor Field Effect Transistor) are miniaturized according to the scaling rule, but the gate or source There is a problem that the resistance of the electrode and the drain increases, and even if the field effect transistor is miniaturized, it cannot operate at a high speed. Therefore, a self-aligned silicide (salicide) technology is currently being studied, that is, a low-resistance silicon oxide layer is formed by self-alignment on the surface of the conductive film constituting the gate and the semiconductor region constituting the source and drain. A metal silicide layer such a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/283H01L21/8238
Inventor 冈田茂业二濑卓也
Owner RENESAS ELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com