Processing method of thin silicon monocrystal polished section

Abstract

The invention relates to a method for producing thin monocrystalline silicon polished wafer. The method comprises the following steps: Step 1, monocrystalline silicon is sliced up by adopting wire cutting; Step 2, a slotting double-face grinder which adopts a stainless steel planetary sheet with an internal circle inlaid with a soft rubber ring is adopted to carry out double-surface grinding on the sliced monocrystalline silicon; Step 3, a technique of acid corrosion thinning is adopted, wherein, the removal amount resulted from acid corrosion is 10 micrometers to 60 micrometers; Step 4, a nanometer grinding technique is adopted, wherein, the removal amount resulted from nanometer grinding is 1 micrometer to 25 micrometers; and Step 5, a wax polishing technique is adopted, wherein, the removal amount resulted from wax polishing is 5 micrometers to 30 micrometers. By adopting a new technical route and a new technical procedure for producing new thin monocrystalline silicon polished wafer, the invention effectively improves TTV level, WARP level, TIR level, STIR level and other levels as well as the finished product rate of the thin monocrystalline silicon polished wafer.

Description

technical field [0001] The invention relates to semiconductor material processing technology and flow design, especially the design of processing technology route and process flow of thin silicon single crystal polished wafer for IC. Background technique [0002] According to the traditional technical route and process flow, since the thinning of the inner circular blade is limited by the strength of the material, not only the slicing loss cannot be reduced, the output rate cannot be increased, but also the warp is large; Due to the hard collision between wafer and silicon wafer, the edge damage rate of silicon wafer is high; due to the deep damage layer of double-sided grinding, the amount of throwing away required for direct polishing after alkali corrosion is large, and the total thickness change (TTV) and flatness (TIR, TIR, STIR) level difference. To sum up, there are three major problems in processing thin polished sheets according to the traditional technical route a...

AI Technical Summary

Problems solved by technology

[0002] According to the traditional technical route and process flow, since the thinning of the inner circular blade is limited by the strength of the material, not only the slicing loss cannot be reduced, the output rate cannot be increased, but also the warp is large; Due to the hard collision between wafer and silicon wafer, the edge damage rate of silicon wafer is high; due to the deep damage layer of double-sided grinding, the amount of throwing away required for direct polishing after alkali corrosion is large, and the total thickness change (TTV) and flatness (TIR, TIR, STIR) level difference

To sum up, there are three major problems in processing thin polished sheets according to the traditional technical route and process flow, namely: 1) high fragmentation rate; 2) low sheet yield; 3) TTV (total thickness variation), Warp (warp degree), Low TIR (total roughness), STIR (local roughness) levels

[0003] According to the traditional technical route and process flow, please refer to figure 1 As shown, since the thinning of the inner circular blade is limited by the strength of the material, not only the slicing loss cannot be reduced, the yield of the chip cannot be increased, but also the warp is large; Hard collision, the edge damage rate of silicon wafer is high; due to the deep damage layer of double-sided grinding, the amount of throwing away required for direct polishing after alkali corrosion is large, and the total thickness variation (TTV) and flatness (TIR, STIR) of the polished wafer are poor.

To sum up, there are three major problems in processing thin polished sheets according to the traditional technical route and process flow, namely: 1) high fragmentation rate; 2) low sheet yield; 3) TTV (total thickness variation), Warp (warp degree), Low TIR (total roughness), STIR (local roughness) levels

Can not meet user requirements

The existence of these problems makes it impossible for thin polishing sheets to enter industrialized production.

[0004] This existing process of polishing silicon wafers not only has a low wafer yield, but also the geometric parameters of the polished wafers are not good, and IC customers first process devices on thick polished wafers, then add a thinning process, and then go through packaging and testing. The process is more complicated

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