Laminated dielectric layer forming method and metal foredielectric layer forming method

Abstract

The invention discloses a laminated dielectric layer forming method, comprising the following steps: providing a substrate with a semiconductor structure; forming a first dielectric layer on the structure; adopting damp-removing process to the first dielectric layer; forming a second dielectric layer on the first dielectric layer which goes through damp-removing process. The invention also discloses a metal foredielectric layer forming method. With the methods of the invention adopted, the stress of the first dielectric layer in the laminated dielectric layer can be restored and maintained, therefore, the expected stress condition of the dielectric layer is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a laminated dielectric layer and a method for forming a pre-metal dielectric layer. Background technique [0002] With the increasing demand for high integration and high performance of ultra-large-scale integrated circuits, semiconductor technology is developing towards a technology node with a feature size of 65nm or even smaller. When the device size is continuously reduced proportionally, the interstitial ability of thin film deposition is also required ( Gap-fill ability) has been further improved. [0003] In the semiconductor manufacturing process, a dielectric layer is usually deposited on the substrate manufactured by the front-end process. In order to obtain reliable device performance, the dielectric layer needs to separate the gaps of the semiconductor structure on the substrate (including gate intervals, shallow trench isolati...

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Problems solved by technology

[0007] However, the problem is that the above-mentioned first dielectric layer and second dielectric layer constituting the pre-metal dielectric layer are manufactured by different equipment. In the actual process flow, the first dielectric layer deposited by HARP SACVD process is relatively loose, and the surface layer has more Si-H dangling bonds exposed to the air are oxidized into Si-OH bonds, which makes the film easy to absorb moisture and gradually loses the tensile stress in the film layer, resulting in the stress value of the entire metal front dielectric layer not meeting the design requirements. As a result, the desired stress state cannot be obtained, which improves the performance of the device

[0008] Similarly, when forming other stacked dielectric layers, because the first dielectric layer is relatively loose or the surface layer has more Si-H dangling bonds, similar moisture absorption will cause stress state changes, so that the designed stress requirements cannot be achieved. question

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