Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Encapsulating structure and encapsulating method for reconfiguring chip

A packaging structure and reconfiguration technology, applied to electrical components, electrical solid devices, circuits, etc., can solve problems such as increased resistance, misalignment, and chip damage

Inactive Publication Date: 2009-12-23
CHIPMOS TECH INC
View PDF2 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This thinned chip is relocated on another substrate, and then multiple chips are formed into a package by injection molding; because the chip is very thin, the package is also very thin, so when the package is detached After the substrate, the stress of the encapsulant itself will cause the encapsulant to warp, increasing the difficulty of the subsequent cutting process
[0006] In addition, after the wafer is diced, when it is reconfigured on another substrate, since the size of the new substrate is larger than the original size, it will not be aligned in the subsequent ball planting process, and the reliability of the packaging structure will be reduced.
For this reason, the present invention provides a soldering pad on which the copper column is formed in advance on the chip, and then the copper column is exposed through the thinning process, so that it can effectively solve the problems of misalignment during ball planting and warping of the encapsulant question
[0007] In addition, during the entire packaging process, there will also be a problem that the manufacturing equipment will generate excessive local pressure on the chip during ball planting, which may damage the chip; at the same time, it may also be caused by the material of the ball planting. The resistance value between the pads becomes larger, which affects the performance of the chip and other issues

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Encapsulating structure and encapsulating method for reconfiguring chip
  • Encapsulating structure and encapsulating method for reconfiguring chip
  • Encapsulating structure and encapsulating method for reconfiguring chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025]The direction of the present invention discussed here is a chip reconfiguration packaging method, in which multiple chips are reconfigured on another substrate and then packaged. In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Clearly, the practice of the present invention is not limited to the specific details of the manner in which chips are stacked that are familiar to those skilled in the art. On the other hand, the well-known chip formation method and detailed steps of chip thinning and other back-end processes are not described in detail to avoid unnecessary limitations of the present invention. However, for the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present inventi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an encapsulating structure and an encapsulating method for reconfiguring a chip. The encapsulating structure comprises a plurality of welding pads configured on an active surface of the chip; first polymer material layers covering on the active surface of the chip and exposing the plurality of the welding pads; a plurality of conductive columns configured among the first polymer material layers and electrically connected with each welding pad; a sealing compound body for coating the chip and exposing the polymer material layers and the conductive columns; a second polymer material layer covering on the first polymer material layers and the sealing compound body and exposing the plurality of the conductive columns; a plurality of fan-out metal wire sections which are configured above the second polymer material layer and of which one ends of the metal wire sections electrically are connected with the conductive columns; and a plurality of conductive elements electrically connected with the other ends of the metal wire sections.

Description

technical field [0001] The invention relates to a semiconductor packaging method, in particular to a packaging method for reconfiguring chips with different sizes and functions. Background technique [0002] Semiconductor technology has developed quite rapidly, so the miniaturized semiconductor chip (Dice) must have diversified functional requirements, so that the semiconductor chip must be configured with more input / output pads (I / O pads) in a small area. O pads), so that the density of metal pins (pins) is also rapidly increased. Therefore, the early lead frame packaging technology is no longer suitable for high-density metal pins; therefore, a ball array (BallGrid Array: BGA) packaging technology has been developed. In addition to the advantages of higher density than lead frame packaging, ball array packaging , and its tin balls are less likely to be damaged and deformed. [0003] With the popularity of 3C products, such as: mobile phone (Cell Phone), personal digital ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/48H01L23/31H01L21/50H01L21/60H01L21/56H01L21/78
CPCH01L2924/01015H01L2924/01023H01L24/19H01L2224/20H01L24/96H01L2924/01079H01L2924/01068H01L2224/04105H01L2924/01033H01L2924/15311H01L2924/01029H01L2924/01078H01L21/6835H01L2924/01094H01L21/568H01L2224/12105H01L2224/19H01L2224/24137H01L2924/3511
Inventor 陈煜仁
Owner CHIPMOS TECH INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products