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Hardware device and method for assisting in processing dynamic bandwidth allocation algorithm

A technology of dynamic bandwidth allocation and hardware device, which is applied to the selection device, selection device, electrical components and other directions of the multiplexing system. and practicality, performance improvement, area reduction effect

Active Publication Date: 2013-01-16
ZTE CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] One: The DBA algorithm is all implemented by hardware. The advantage of using hardware to implement DBA is that the performance is relatively high and can meet the bandwidth requirements of the system, but there is also a fatal shortcoming, that is: if FPGA (Field Programmable Gate Array, programmable logic Array) to implement the DBA algorithm will take up a lot of logic resources and increase the implementation cost; if ASIC is used to implement the DBA algorithm, once the DBA algorithm part is updated, it will not be able to be changed
[0005] Two: The DBA algorithm is all implemented by software. Because the DBA algorithm is more complicated, it is also very large to implement by software, and the workload of CPU calculation is also very large.
And in the actual GPON system, multi-PON (passive optical network) port mode is often adopted, which requires multi-channel DBA algorithm (considering that one PON port corresponds to one-way DBA algorithm). For such a complex multi-channel DBA algorithm, the CPU Systems are often difficult to handle
Since the core software of the DBA needs to be processed, the hardware device should contain a CPU. For early PON chips, it is generally realized by using an off-chip CPU+protocol chip. Since an off-chip CPU is used, there must be many peripherals around the CPU. Not only does it take up a lot of PCB area, but the performance of the CPU system is also difficult to improve, and the performance required by GPON MAC is higher, the downlink requirement reaches 2.5Gbits / s, and the uplink requirement reaches 1.25Gbits / s, thus reducing the uplink and downlink message processing efficiency

Method used

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Embodiment Construction

[0027] The present invention builds an embedded PowerPc CPU subsystem based on the embedded PowerPc405 (abbreviated as PPC) hard core in the XILINX V4 FX100FPGA. After the subsystem is powered on and completes boot (boot), it first initializes the system with the support of the operating system and software, completes the configuration and setting of the GPON OLT MAC, and completes the optical terminal side hardware logic module (OLT) The network unit (ONU) performs related configuration and initialization (including assisting in ranging, assisting in obtaining the S / N of the ONU, and setting the power of the ONU, etc.). After the system enters normal operation, it monitors the working status of OLT and ONU, assists in the processing of alarms and errors of OLT and ONU, and assists the hardware in the bandwidth allocation of the DBA algorithm of TCONT (Transmission Container) in the ONU. In addition, the PPC system also assists the OLT to complete the key exchange with the ONU...

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Abstract

The invention discloses a hardware device and a method for assisting in processing a dynamic bandwidth allocation (DBA) algorithm. The hardware device comprises a hardware logic module, a register interface control module, a synchronous dynamic RAM controller module, a FLASH controller module, an interrupt processor module, a universal asynchronous receiver / transmitter controller module, and a master-slave communication module, a master-slave communication interface module, a PowerPc CPU module, a processor bus module, a processor bus-to-on-chip- peripheral-bus bridge module and an on chip peripheral bus module which are orderly connected, wherein the PowerPc CPU module is used for processing and controlling data acquired by the hardware logic module, is connected with a master CPU interface in the hardware logic module through the master-slave communication module to finish communications between an embedded CPU and a master CPU, and controls and configures a register in the hardwarelogic module and the report and the allocation of the dynamic bandwidth allocation algorithm through a register interface module. The hardware device and the method for assisting in processing the dynamic bandwidth allocation algorithm can flexibly process the DBA core algorithm and save the cost.

Description

technical field [0001] The invention relates to the field of network access data communication, in particular to a hardware device and method for assisting in processing a Dynamic Bandwidth Allocation (DBA) algorithm. Background technique [0002] In the Gigabit Passive Optical Network (GPON) system, DBA is proposed to solve how to maximize the effective use of the bandwidth of the GPON system. The current multi-service GPON and EPON (Ethernet Passive Optical Networks, Ethernet Passive Optical Networks) are required to ensure the QoS (Quality of Service, Quality of Service) of various services, so a very sensitive bandwidth allocation mechanism is required. How long the scheduling period is to complete a bandwidth allocation and bandwidth allocation algorithm will directly affect the uplink bandwidth utilization rate of the GPON system and the service quality of various services. [0003] Currently, in terms of architecture, there are mainly two ways to implement the DBA al...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/917H04Q11/00H04L47/76
Inventor 罗国强
Owner ZTE CORP
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