Embedded programmable memory based on memory IP core

Abstract

The invention discloses an embedded programmable memory based on memory IP core, which provides programmable mechanism, enables users to design the bit wide, work mode and synchronous / asynchronous output of the memory, and supports the work modes, including packet mode, single port, simple dual port and true dual port. The invention adopts an additional register to buffer conflicting data and address, utilizes the bit zone of the data bit and the read-write conflict detection and protection mechanism to realize the programmable memory; the design convenience is realized and the functional flexibility is also realized, and the functions of conventional memory are greatly extended; compared with conventional programmable memory technology, the embedded programmable memory has great improvements on speed, area, power consumption and reliability.

Description

Technical field [0001] The invention relates to the technical field of microelectronics, in particular to an embedded programmable memory based on a memory intellectual property core. Background technique [0002] In the design of electronic systems, memory is used more and more widely. When designing a System-on-a-Chip (SoC), it is often necessary to use embedded memory. There are two ways to design embedded memory in SoC, one is full custom design; the other is to use the memory intellectual property core (Intellectual Property Core, IP Core) provided by a third-party chip design service company (referred to as a third party, such as Artisan) To design. The two methods have their own advantages and disadvantages. The fully customized design has good performance, rich functions, but high technical requirements and long design cycle; the IP core-based method is easy to implement, and the design cycle is short, but it is subject to some limitations of IP cores provided by third ...

AI Technical Summary

Problems solved by technology

[0003] After the dual-port SRAM IP core (DP-SRAM IP Core, hereinafter referred to as IP core or IP) is generated, the data bit width of its two ports has been fixed and cannot be changed by programming; its clock-based read The write protection mechanism (such as the DPCCM mechanism in the Artisan document ) can ensure that the write operation is protected when reading and writing the same row address at the same time, but it cannot guarantee the reliability of the read operation

[0004] In previous technologies (such technologies usually adopt such as figure 1 Solution: Set two sets of data bypass and data latch, use a set of cache registers on both ports, and exchange data between the cache registers of the two ports, it is necessary to cache the address of all bits of the address bus instead of part address, the output logic needs to be compared with the full address, and the output data is output after a large combinational logic interleaving), and the Bypass bypass and latch mode are used to provide some programmable functions, but the design is complex and the critical path of the signal long (such as figure 1 Medium and long critical paths (PATH1 and PATH2), work slowly

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