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System for testing system internuclear wiring fault on integrated circuit chip and method thereof

A system-on-chip, integrated circuit technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problem of no inter-core wiring fault and intra-core fault testing, test system hardware structure and test search mechanism are not involved, etc. question

Inactive Publication Date: 2012-11-07
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The current research on SOC connection fault testing mainly focuses on the optimization algorithm of vector compression and test structure, but the hardware structure of the test system and the test search mechanism are not involved, and there is no research on the inter-core connection fault and the core fault test. consider together

Method used

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  • System for testing system internuclear wiring fault on integrated circuit chip and method thereof
  • System for testing system internuclear wiring fault on integrated circuit chip and method thereof
  • System for testing system internuclear wiring fault on integrated circuit chip and method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0039] Embodiment one: see figure 1 , the test system for the fault of the connection between the cores of the integrated circuit system on chip is composed of a parallel test bus 1, an edge packaging unit link 2, a clock control unit 3, an IP core selection decoding unit 4 and an IP core connection signal integrity selection decoding Unit 5 is formed, it is characterized in that: described parallel test bus 1 has a group of external test bus signal input pins (TAMI) and a group of external test bus signal output pins (TAMO), and in-chip output connection internal described edge Packaging unit link 2; the edge packaging unit link 2 has a group of external system-on-chip function signal input pins PI or system-on-chip function signal output pin PO and an external edge packaging unit link enable signal input pin WSE, And in-chip output connects described parallel test bus 1; Described clock control unit 3 has an external system work clock signal input pin CLK, an external test e...

Embodiment 2

[0040] Embodiment 2: This embodiment is the same as Embodiment 1, and the special features are as follows: see figure 1 , the parallel test bus 1 has a group of external test bus signal input pins TAMI and a group of external test bus signal output pins TAMO, and the on-chip output is connected to the internal edge packaging unit link 2; each edge packaging unit link 2 There is a group of external system-on-chip function signal input pins PI or system-on-chip function signal output pins PO and an external edge package unit link enable signal input pin WSE, while the on-chip output is connected to the parallel test bus 1; clock control Unit 3 has an external system working clock signal input pin CLK, an external test enable signal input pin TEN, an external IP core test clock signal input pin IPTCLK and an external edge package unit link test clock signal input pin WCLK, and the internal output of the chip is connected to each IP core and the edge packaging unit link 2 of the s...

Embodiment 3

[0041] Embodiment three: the test method of the wiring fault between the cores of the integrated circuit system on chip is: see figure 2 , the above-mentioned IP core inter-core connection failure test search mechanism 6 starts to work when TEN=1. Each IP core edge packaging unit link 2 is connected to the parallel test bus 1 . First configure the IP core selection signal SelectIP i And the IP core signal integrity selection signal SISelIP i . According to the IP core selection signal that IP core selection decoding unit 5 produces, select a certain IP iAt the same time as the core, the corresponding edge encapsulation unit link 3 is also selected i , and work together with the clock control unit 4. At this time, firstly, the edge packaging unit link 2 can be tested through the TAMI port of the parallel test bus 1. i Add the corresponding IP core-core connection fault test code, and shift this test code to the edge packaging unit link 2 i The last edge packaging unit; ...

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Abstract

The invention relates to a system for testing a system internuclear wiring fault on an integrated circuit chip and a method thereof. The system comprises a circuit structure which is added for perfecting the IP internuclear wiring fault test and the IP intranuclear fault test in a system on the integrated circuit chip and a test inquiring mechanism which runs on the basis of the circuit structure. The invention can test the IP internuclear wiring of the system on the integrated circuit chip. The fault types of the test comprises the solid-zero fault, the solid-solid fault, the open circuit fault, the short circuit fault, the delaying fault and the noise fault. By adding a hardware structure, the invention decomposes a scanning chain of edge packing units, thereby making the best of a testbuss and shortening the test time; with the output type edge packing unit, the invention automatically generates a test vector; with the input type edge packing unit, the invention further shortens the test time. The structure is compatible with the intranuclear test structure, thereby realizing the higher flexibility, making the best of the test resource, and further improving the fault coveragerate of the system of the whole integrated circuit chip. The invention is simple in circuit structure, convenient in test inquiring mechanism, and suitable for the various systems on the integrated circuit chips which are designed and built with the IP multiplexing technology.

Description

technical field [0001] The invention relates to an integrated circuit fault testing system and method, in particular to a testing system and method for inter-core connection faults applied to an integrated circuit system on chip (SOC System on a Chip). Background technique [0002] Now integrated circuit (IC) designers are developing towards better cost advantages and time-to-market, and seize market opportunities with the fastest speed and the best cost performance. The existence of these needs urgently makes multiple functions integrated into one chip. become possible, the system on a chip (SOC System on a chip) came into being. From an engineering point of view, integrating more functions into a single chip can indeed achieve cost savings, but from a testing point of view, a large number of SOC pins, multiple cores with different Features such as test vectors make the test of SOC much more complicated than that of a single chip. How to reduce the test difficulty and tes...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/02
Inventor 李娇张金艺杨晓冬蔡万林施慧张冬黄徐辉翁寒一丁梦玲
Owner SHANGHAI UNIV