Wafer level chip scale packaging structure with low substrate resistance and manufacturing method thereof

Abstract

The invention discloses a wafer level chip scale packaging structure with low substrate resistance. The packaging structure comprises a semiconductor chip and a conducting reinforcing member, wherein the semiconductor chip comprises a semiconductor chip upper surface and a semiconductor chip lower surface; the semiconductor chip upper surface is provided with a plurality of integrated circuit chips, a plurality of under bump metallization (UBM) and a plurality of welding balls which are arranged on the UBM and are used for chip connection; the conducting reinforcing member comprises a conducting reinforcing member upper surface; the conducting reinforcing member upper surface is provided with a first metal layer; and the first metal layer of the conducting reinforcing member and the semiconductor chip lower surface are bonded together in the manufacturing process. The wafer level chip scale packaging structure and the manufacturing method have the beneficial effects of improving the chip substrate conductivity and reducing the substrate resistance and the transverse on-resistance on the one hand, and improving the reliability of the chip while reducing the package scale and ensuring the wafer and the chip not to be easily damaged in the process operation on the other hand.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method, in particular to a wafer-level chip size packaging with low substrate resistance and a manufacturing method thereof. Background technique [0002] Wafer Level Chip Scale Packaging (WLCSP) is an integrated circuit chip packaging technology, which is different from the traditional chip packaging method (cutting first, then packaging and testing, and at least 20% of the volume of the original chip after packaging) , this latest technology is to carry out packaging and testing on the wafer first, and then cut into IC particles one by one, so the volume after packaging is equal to the original size of the IC die. For wafer-level chip packaging, the packaging area is the same as The chip area ratio is less than 1.2. [0003] Recently developed electronic devices such as mobile phones, laptop computers, video cameras, personal digital assistants, and other similar device...

AI Technical Summary

Problems solved by technology

The wafer-level chip size package has the advantages of small size, light weight, good electrical conductivity, and simple process. However, the conductive column only solves the conductive problem in the vertical direction of the chip. For the electrical connection in the horizontal direction of the substrate, can't work

[0005] For double-diffused metal-oxide-semiconductor (DMOS), especially for wafer-level chip-scale packages with a common-drain dual-chip structure, such as figure 1 As shown, the conductive paths are shown by the arrows in Figure 1, which are path a, path b, and path c, respectively, where path a and c are substrate resistances. In wafer-level chip-scale packaging, the substrate resistance can be close to the entire 50% of the on-resistance, due to the small package size of the chip itself, this ratio obviously greatly affects the performance of the chip. In addition, if the substrate resistance is reduced by reducing the substrate thickness, due to the thin thickness of the wafer, the manufacturing And during the operation, it is very easy to cause damage to the wafer

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