Grid dielectric layer manufacturing method
A technology of gate dielectric layer and manufacturing method, which is applied in the field of gate dielectric layer manufacturing, can solve problems such as edge trenches that are prone to appear on the edge of a shallow trench isolation structure, and achieve the goals of reducing static leakage current, uniform thickness, and preventing edge leakage Effect
Active Publication Date: 2013-02-27
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0010] The invention provides a method for manufacturing a gate dielectric layer to solve the problem that side grooves are prone to appear at the edge of a shallow trench isolation structure in the existing method for manufacturing a gate dielectric layer, and the invention does not require a long-term heat treatment process, Improved performance of semiconductor devices
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[0022] The core idea of the present invention is to provide a method for manufacturing a gate dielectric layer, which does not form a sacrificial oxide layer after forming a shallow trench isolation structure, and therefore does not require a long-term heat treatment process, which can avoid generation of Stress reduces the static leakage current of the silicon wafer; and, since the present invention does not form a sacrificial oxide layer, the step of removing the sacrificial oxide layer is omitted after the formation of the well region, which can ensure that the edge region of the shallow trench isolation structure will not be damaged. Corrosion, so as to avoid side trenches in the edge region of the shallow trench isolation structure, can ensure the formation of a gate dielectric layer with a uniform thickness, and improve the performance of the semiconductor device.
[0023] Please refer to figure 2 , which is a flow chart of a gate dielectric layer manufacturing method...
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The invention discloses a grid dielectric layer manufacturing method, comprising the following steps: providing a semiconductor substrate; forming a shallow trench isolation structure in the semiconductor substrate; executing an ion implantation process; forming a well region in the semiconductor substrate; and forming a grid dielectric layer on the semiconductor substrate. In the method, after the shallow trench isolation structure is formed, no sacrificial oxide layer is formed, thus a long-time heat treatment process is not needed; and in the method, the step of removing the sacrificial oxide layer is omitted, thus avoiding a side ditch from appearing on the marginal area of the shallow trench isolation structure, and improving the performance of a semiconductor device.
Description
technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a gate dielectric layer. Background technique [0002] In the field of integrated circuit manufacturing, metal oxide semiconductor field effect transistors (MOSFETs) are commonly used in the manufacturing process of ultra large scale integrated circuits (ULSI). With the continuous improvement of semiconductor manufacturing technology, the size of the gate of the metal oxide semiconductor field effect transistor is also getting smaller and smaller, and the requirements for the manufacturing process of the gate dielectric layer are also getting higher and higher. [0003] For details, please refer to Figure 1A-1E , which is a schematic cross-sectional view of structures corresponding to each step of the existing gate dielectric layer manufacturing method. [0004] refer to Figure 1A First, a semiconductor substrate 10 is provided, and t...
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IPC IPC(8): H01L21/283H01L21/762
Inventor 孙鹏刘丽丽仇峰
Owner SEMICON MFG INT (SHANGHAI) CORP