Method for forming pre-metal dielectric layer

Abstract

The invention discloses a method for forming a pre-metal dielectric layer, which comprises the following steps of: providing a semiconductor substrate with an N-channel metal oxide semiconductor (NMOS) transistor and a P-channel metal oxide semiconductor (PMOS) transistor; depositing a buffer oxide layer on the semiconductor substrate; depositing a first etched barrier layer with high tensile stress on the buffer oxide layer; depositing a first pre-metal dielectric layer with the tensile stress; depositing a metal hard mask layer; coating a layer of photoresist on the hard mask layer so as to perform photoetching on a PMOS region and an NMOS region until the PMOS region is exposed on the first etched barrier layer, and moreover, reserving the first pre-metal metal dielectric layer on the surface of the NMOS region; depositing a second etched barrier layer with the high tensile stress on the surface of a semiconductor device; depositing a second pre-metal dielectric layer with the tensile stress on the second etched barrier layer; and performing grinding and polishing on the second pre-metal dielectric layer. Technologically, the method for forming the pre-metal dielectric layer has relatively simple steps, and meanwhile, the carrier mobility of NMOS / PMOS can be increased.

Description

technical field [0001] The invention relates to the field of microelectronics, in particular to a method for forming a pre-metal dielectric layer. Background technique [0002] As the characteristic line width of integrated circuits shrinks below 90nm, people gradually introduce high-stress silicon nitride technology to improve the electrical mobility of carriers. By depositing high-tension and high-voltage stress silicon nitride on N / PMOS as a contact etch stop layer (Contact Etch Stop Layer, CESL), especially below the 65nm process, in order to improve the electrical mobility of N / PMOS at the same time, sometimes It is necessary to simultaneously deposit high pull and high voltage stress silicon nitride on different MOS. After the deposition of the etching barrier layer is completed, the pre-metal dielectric layer needs to be deposited, which is currently deposited by high-density plasma (HDP CVD), or by high aspect ratio process (HARP, High Aspect Ratio Process). to dep...

AI Technical Summary

Problems solved by technology

[0009] Utilize the PMD layer prepared by above-mentioned existing method to be a kind of among HDP thin film or HARP thin film, but, because HDP and HARP thin film stress state are opposite (HDP is compressive stress, and stress range is at 100Mpa~300MPa; HARP is tensile stress, Stress ranges from 100Mpa to 200MPa), they can only help improve the performance of one type of transistor

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