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Double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)

A hybrid crystal orientation and nanowire technology, applied in nanotechnology, nanotechnology, nanotechnology for information processing, etc., can solve problems such as ensuring bond strength

Active Publication Date: 2014-12-10
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The core issue is whether the bonding strength can be guaranteed after lowering the annealing temperature

Method used

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  • Double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)
  • Double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)
  • Double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)

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Embodiment Construction

[0040] The present invention will be explained in detail below in conjunction with the accompanying drawings.

[0041] Please refer to Figure 1(a), Figure 1(b), Figure 1(c), and combined figure 2 , Fig. 1(a) is a schematic top view structure diagram of the double-layer isolation semiconductor nanowire MOSFET of the present invention. Figure 1(b) is a schematic cross-sectional structure diagram of Figure 1(a) along the X-X' direction. Figure 1(c) is a schematic diagram of the cross-sectional structure of Figure 1(a) along the Y-Y' direction. The double-layer isolation mixed crystal orientation semiconductor nanowire MOSFET 1 includes a semiconductor substrate 10, a first MOSFET 11, a second MOSFET 12, and an isolation dielectric layer 13 arranged between the first MOSFET 11 and the second MOSFET 12 , the buried oxide layer 14 disposed between the first MOSFET 11 and the semiconductor substrate 10, disposed on the first source region 110, the first drain region 111 and the fir...

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Abstract

The invention provides a double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET) which comprises a first MOSFET, an isolation medium layer and a second MOSFET which are sequentially formed on a semiconductor lining. A first source electrode liner, a first drain electrode liner, a second source electrode liner and a second drain electrode liner of the first MOSFET and the second MOSFET are germanium silicon layers. A carbon silicon layer grows on a first source electrode area and a first drain electrode area, and a germanium silicon layer grows on a second source electrode area and a second drain electrode area. A wet method is utilized to etch the SiGe layers, so that the manufacture process of a cavity layer under a silicon nanowire area can be well controlled. The MOSFET increases mobility ratio of carriers and electrons of an N-type metal oxide semiconductor field effect transistor (NMOSFET) and mobility ratio of carrier cavities of a power metal oxide semiconductor field effect transistor (PMOSFET) and increases current drive capability of a complementary metal oxide semiconductor (CMOS). The first MOSFET and the second MOSFET can be independently used for conducting process debugging.

Description

technical field [0001] The invention relates to the technical field of semiconductor field effect transistors, in particular to a double-layer isolation mixed crystal orientation strained nanowire MOSFET. Background technique [0002] It has always been the goal pursued by the development of microelectronics industry to increase the working speed and integration of chips and reduce the power consumption density of chips by reducing the size of transistors. In the past forty years, the development of microelectronics industry has been following Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few layers thick of oxygen atoms. It is difficult to improve performance by reducing the size of traditional field effect transistors. Channel effect and gate leakage current deteriorate the switching performance of the transistor. [0003] Nanowire Field Effect Transistor (NWFET, Nanowire MOSFET) is expec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L29/775H01L29/08B82Y10/00
Inventor 黄晓橹
Owner SHANGHAI HUALI MICROELECTRONICS CORP