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Preparation method of double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)

A technology of mixing crystal orientation and nanowires, which is applied in transistors, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve problems such as guaranteed bonding strength

Active Publication Date: 2015-03-18
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The core issue is whether the bonding strength can be guaranteed after lowering the annealing temperature

Method used

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  • Preparation method of double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)
  • Preparation method of double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)
  • Preparation method of double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET)

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Embodiment Construction

[0040] Hereinafter, the present invention will be explained in detail with reference to the drawings.

[0041] Please refer to Figure 1(a), Figure 1(b), Figure 1(c), and the combination figure 2 , Figure 1 (a) shows a schematic top view of the double-layer isolation semiconductor nanowire MOSFET of the present invention. Fig. 1(b) is a schematic cross-sectional view of Fig. 1(a) along the X-X' direction. Fig. 1(c) is a schematic cross-sectional view of Fig. 1(a) along the Y-Y' direction. The double-layer isolation hybrid crystal orientation semiconductor nanowire MOSFET 1 includes a semiconductor substrate 10, a first MOSFET 11, a second MOSFET 12, and an isolation dielectric layer 13 provided between the first MOSFET 11 and the second MOSFET 12 , The buried oxide layer 14 provided between the first MOSFET 11 and the semiconductor substrate 10 is provided in the first source region 110, the first drain region 111 and the first gate of the first MOSFET 11 The first insulating di...

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Abstract

The invention provides a double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET) which comprises a first MOSFET, an isolation medium layer and a second MOSFET which are sequentially formed on a semiconductor lining. A first source electrode liner, a first drain electrode liner, a second source electrode liner and a second drain electrode liner of the first MOSFET and the second MOSFET are germanium silicon layers. A germanium silicon layer grows on a first source electrode area and a first drain electrode area, and a carbon silicon layer grows on a second source electrode area and a second drain electrode area. A wet method is utilized to etch the SiGe layers, so that the manufacture process of a cavity layer under a silicon nanowire area can be well controlled. The MOSFET increases mobility ratio of carriers and electrons of an N-type metal oxide semiconductor field effect transistor (NMOSFET) and mobility ratio of carrier cavities of a power metal oxide semiconductor field effect transistor (PMOSFET) and increases current drive capability of a complementary metal oxide semiconductor (CMOS). The first MOSFET and the second MOSFET can be independently used for conducting process debugging.

Description

Technical field [0001] The invention relates to the technical field of semiconductor field effect transistors, in particular to a method for preparing a double-layer isolation hybrid crystal orientation strained nanowire MOSFET. Background technique [0002] It has always been the goal pursued by the development of the microelectronics industry to improve the working speed and integration of the chip and reduce the power density of the chip by reducing the size of the transistor. In the past 40 years, the development of the microelectronics industry has been following Moore's Law. At present, the physical gate length of field-effect transistors is close to 20nm, and the gate dielectric is only a few oxygen atomic layers thick. There are some difficulties in improving performance by reducing the size of traditional field-effect transistors. This is mainly due to the small size of the short trench. The channel effect and gate leakage current deteriorate the switching performance o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/10H01L21/336H01L27/092H01L21/8238
Inventor 黄晓橹
Owner SHANGHAI HUALI MICROELECTRONICS CORP