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Bi-polycrystal strain SiGe SOI (Silicon On Insulator) Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and preparation method thereof

An integrated device, dual polycrystalline technology

Inactive Publication Date: 2012-10-10
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, when the feature size is less than 100nm, due to problems such as tunneling leakage current and reliability, the traditional gate dielectric material SiO 2 Unable to meet the requirements of low power consumption; the short channel effect and narrow channel effect of nanometer devices are becoming more and more obvious, which seriously affects the device performance; traditional lithography technology cannot meet the shrinking lithography precision
Therefore, traditional Si-based process devices are increasingly difficult to meet the needs of design

Method used

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  • Bi-polycrystal strain SiGe SOI (Silicon On Insulator) Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0118] Embodiment 1: The preparation of a double polycrystalline, strained SiGe SOI BiCMOS integrated device with a channel length of 22nm, the specific steps are as follows:

[0119] Step 1, epitaxial growth.

[0120] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0121] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 .

[0122] Step 2, deep trench isolation preparation.

[0123] (2a) Deposit a layer of SiO on the surface of the substrate at 600°C by chemical vapor deposition (CVD) 2 ;

[0124] (2b) In the photolithographic isolation area, a deep groove with a depth of 2.5 μ...

Embodiment 2

[0179] Embodiment 2: The preparation of a double polycrystalline, strained SiGe SOI BiCMOS integrated device with a channel length of 130nm, the specific steps are as follows:

[0180] Step 1, epitaxial growth.

[0181] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0182] (1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 .

[0183] Step 2, deep trench isolation preparation.

[0184] (2a) Deposit a layer of SiO on the surface of the substrate at 700 °C by chemical vapor deposition (CVD) 2 ;

[0185] (2b) In the photolithographic isolation area, a deep groove with a depth of 3 μm is etch...

Embodiment 3

[0240] Embodiment 3: the preparation channel length is the dual polycrystalline, strained SiGe SOI BiCMOS integrated device of 350nm, and specific steps are as follows:

[0241] Step 1, epitaxial growth.

[0242] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0243] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 .

[0244] Step 2, deep trench isolation preparation.

[0245](2a) Deposit a layer of SiO on the surface of the substrate at 800°C by chemical vapor deposition (CVD) 2 ;

[0246] (2b) In the photolithographic isolation area, a deep groove with...

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Abstract

The invention discloses a bi-polycrystal strain SiGe SOI (Silicon On Insulator) Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: growing an N type Si epitaxial layer on an SOI substrate to be taken as a collector region of a bipolar device, preparing a deep-trench isolator, then sequentially preparing base polycrystal, a base region and an emitter region to form a SiGe HBT (Heterojunction Bipolar Transistor) device; and growing strain SiGe material on the substrate, conducting photoetching on the active regions of an NMOS (N-Channel Metal Oxide Semiconductor) device and a PMOS (P-Channel Metal Oxide Semiconductor) device, injecting P type ions in the region of the NMOS device to prepare virtual grid, conducting self alignment to generate source-drain regions of the NMOS device and the PMOS device, removing the virtual grid, preparing a grid medium and wolfram (W) to form a grid electrode, conducting photoetching on a lead wire to form the bi-plycrystal strain SiGe SOI Bi CMOS integrated device and a circuit. Due to the preparation of the bi-plycrystal strain SiGe SOI Bi CMOS integrated circuit, the performances of a conventional analogue integrated circuit and a digital-analogue mixed integrated circuit are improved greatly.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a double-polycrystalline, strained SiGe SOI BiCMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuit technology is the core technology of high-tech and information industries, and has become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength, while microelectronic technology represented by integrated circuits is the key to semiconductor technology. The semiconductor industry is the basic industry of the country. The reason why it develops so fast is not only the huge contribution of technology itself to economic development, but also its wide applicability. [0003] Gordon Moore, one of the founders of Intel, proposed "Moore's Law" in 1965, which states that the number of transistors on an integrat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 张鹤鸣周春宇宋建军宣荣喜胡辉勇舒斌戴显英郝跃
Owner XIDIAN UNIV
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