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Method for forming semiconductor package structure

A packaging structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid device manufacturing, electric solid devices, etc., can solve problems such as chip failure, solder ball 7 falling off, etc., and achieve the effect of improving the bonding force

Active Publication Date: 2016-11-23
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in the above packaging structure, the solder ball 7 is easy to fall off from the top surface of the copper pillar 5, thereby causing chip failure.

Method used

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  • Method for forming semiconductor package structure
  • Method for forming semiconductor package structure
  • Method for forming semiconductor package structure

Examples

Experimental program
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Effect test

no. 1 example

[0022] The first embodiment of the present invention firstly provides a method for forming a semiconductor package structure, please refer to figure 2 , which is a schematic flow chart of the method for forming the semiconductor package structure, specifically including:

[0023] Step S101, providing a chip, the surface of the chip has pads, and an insulating layer exposing the pads is formed on the surface of the chip;

[0024] Step S102, forming a first passivation layer on the surface of the insulating layer, the first passivation layer covering part of the pad;

[0025] Step S103, forming an electroplating seed layer on the surface of the pad and the first passivation layer, forming a second mask layer on the surface of the electroplating seed layer, forming a penetrating through the second mask layer in the second mask layer the second opening of the film layer;

[0026] Step S104, using an electroplating process to form a columnar electrode in the second opening;

[...

no. 2 example

[0075] The second embodiment of the present invention provides another method for forming a semiconductor package structure. For details, please refer to Figure 13 to Figure 23 , is a schematic cross-sectional structure diagram of the formation process of the semiconductor package structure according to the second embodiment of the present invention.

[0076] Please refer to Figure 13 , provide a chip 200, the surface of the chip 200 has a bonding pad 201, and an insulating layer 210 exposing the bonding pad 201 is formed on the surface of the chip 200. The pad 201 , the subsequently formed electroplating seed layer on the surface of the pad, and the rewiring metal layer on the surface of the electroplating seed layer constitute a metal interconnection structure.

[0077] Please refer to Figure 14 , form an electroplating seed layer 220 on the surface of the pad 201 and the insulating layer 210, form a third mask layer 225 on the surface of the electroplating seed layer 2...

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Abstract

Disclosed is a method for forming semiconductor packaging structures. The method comprises that a columnar electrode is formed on the surface of a metal interconnection structure, and the periphery of the bottom of the columnar electrode exposes part of the metal interconnection structure; a diffusion barrier layer is formed on surfaces of the side wall and the top of the columnar electrode and the metal interconnection structure exposed on the periphery of the bottom of the metal interconnection structure; and a solder ball is formed on the surface of the diffusion barrier layer and is at least covered on surfaces of the top and the side walls of the columnar electrode. As the diffusion barrier layer is formed on surfaces of the side wall and the top of the columnar electrode and the metal interconnection structure exposed on the periphery of the bottom of the metal interconnection structure, the columnar electrode is separated from the solder ball, a tin and copper interface alloy compound cannot be formed, and the solder ball cannot fall from the columnar electrode easily; and the solder ball is at least covered on the surfaces of the top and the side walls of the columnar electrode, so that external forces cannot shift the solder ball which is not easy to fall off the surface of the columnar electrode.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a method for forming a highly reliable semiconductor packaging structure. Background technique [0002] In the current semiconductor industry, electronic packaging has become an important aspect of industry development. After decades of packaging technology development, the traditional peripheral wiring packaging and ball grid array packaging technology is increasingly unable to meet the current high-density, small-size packaging requirements, wafer-level chip packaging (Wafer-Level Chip Scale Packaging) Technology, WLCSP) technology has become a popular packaging method. [0003] Please refer to figure 1 , is a schematic cross-sectional structure diagram of a packaging structure of an existing wafer-level chip packaging method, including: a silicon substrate 1, an insulating layer 2 located on the surface of the silicon substrate 1, the insulating layer 2 has an opening, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48
CPCH01L2224/0361H01L2224/03912H01L2224/1147H01L2224/1182H01L2224/11903
Inventor 林仲珉陶玉娟
Owner NANTONG FUJITSU MICROELECTRONICS