Manufacture method of isolation type power transistor

Abstract

The invention discloses a manufacture method of an isolation type power transistor. By the manufacture method, insulating medium layers formed on the top of gate polycrystalline silicon and spacer medium layers formed on the side faces of the insulating medium layers serve as hard masks for etching to form isolation layer trenches among devices, and an insulated isolation layer can be formed among transistors without adding extra masks, so that density of the transistors in a chip cannot be decreased, and mutual interference of the devices can be weakened. Increase of the size of the transistors and increase of density of transistors in the chip are benefited, and powder devices lower in breakover resistance and saturation voltage drop and higher in current driving capacity can be obtained. Manufacture cost can be further reduced as adding of extra masks is not needed.

Description

technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing method of an isolated power transistor. Background technique [0002] In the application of power and high-voltage devices, it is hoped that the on-resistance of the transistor will be smaller, the saturation voltage drop will be lower, and the current driving capability will be greater. How to integrate more devices within a certain chip area is particularly important. However, with the increase of device density, the distance between transistors in chip cells is getting smaller and smaller, and the crosstalk between adjacent devices may affect each other, thereby affecting chip performance. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a method for manufacturing isolated power transistors, which can form an insulating isolation layer between transistors without...

AI Technical Summary

Problems solved by technology

However, with the increase of device density, the distance between transistors in chip cells is getting smaller and smaller, and the crosstalk between adjacent devices may affect each other, thereby affecting chip performance.

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