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Method for forming gate dielectric layer and MOS transistor

Active Publication Date: 2016-08-31
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the thickness of the gate dielectric layer continues to decrease, it is necessary to implant nitrogen ions on the surface of the gate dielectric layer made of silicon dioxide by using a plasma process to increase the K (dielectric constant) value of the gate dielectric layer; however, in nitrogen During the ion implantation process, the K value shifts due to uneven distribution, and the nitrogen ions cause damage to the semiconductor substrate, which affects the performance of the semiconductor device subsequently formed on the semiconductor substrate

Method used

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  • Method for forming gate dielectric layer and MOS transistor
  • Method for forming gate dielectric layer and MOS transistor
  • Method for forming gate dielectric layer and MOS transistor

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Experimental program
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Embodiment 1

[0040] Figure 3 to Figure 5 It is a schematic structural diagram of the first embodiment of forming a high-K gate dielectric layer according to the present invention.

[0041] Such as image 3 As shown, a semiconductor substrate 100 is provided; an isolation region (not shown) and an active region between the isolation regions are formed in the semiconductor substrate 100; silicon dioxide is formed on the semiconductor substrate 100 in the active region Layer 102.

[0042] In this embodiment, the semiconductor substrate 200 can be selected from a silicon substrate, silicon on insulating layer (SOI), or other materials, such as III-V compounds such as gallium arsenide.

[0043] In this embodiment, the silicon dioxide layer 102 is formed by thermal oxidation or chemical vapor deposition.

[0044] Such as Figure 4 As shown, the process parameters are set, and the nitrogen-containing gas introduced into the plasma chamber is plasmaized under the condition of high power and h...

Embodiment 2

[0054] Figure 6 to Figure 10 It is a schematic structural diagram of the second embodiment of forming a high-K gate dielectric layer according to the present invention.

[0055] Such as Figure 6 As shown, a semiconductor substrate 200 is provided; isolation regions (not shown) and active regions located between the isolation regions are formed in the semiconductor substrate 200; silicon dioxide is formed on the semiconductor substrate 200 in the active region Layer 202.

[0056] In this embodiment, the silicon dioxide layer 202 is formed by thermal oxidation or chemical vapor deposition.

[0057] Such as Figure 7 As shown, the process parameters are set, and the nitrogen-containing gas introduced into the plasma chamber is plasmaized under the condition of high power and high duty ratio for the first time to generate the first nitrogen ions 204; the first nitrogen ions 204 are combined with the The silicon layer 202 reacts to form a silicon oxynitride layer 206 on the s...

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Abstract

Disclosed are forming methods of a gate medium layer and metal oxide semiconductor (MOS) transistor. The forming method of the gate medium layer includes that a semiconductor substrate is provided. A silica layer is formed on the semiconductor substrate. Nitrogen ion is injected on the surface of the silica layer under the condition of at least one-time high power high duty ratio. The nitrogen ion is injected on the surface of the silica layer before or after the nitrogen ion is injected under the conditions of each-time high power high duty ratio under the conditions of low power low duty ratio or the low power high duty ratio or high power low duty ratio. According to the forming method of the gate medium layer and the MOS transistor, the fact that the distribution of nitrogen element of the nitrogen silicon oxynitride is close to the surface is guaranteed. The proportion on the surface is large. The damage of the semiconductor substrate by the nitrogen ion is avoided. The performance of the semiconductor device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a gate dielectric layer and a MOS transistor. Background technique [0002] With the continuous improvement of the integration level of semiconductor devices and the reduction of technology nodes, the traditional gate dielectric layer continues to become thinner, and the leakage of transistors increases accordingly, causing problems such as waste of power consumption of semiconductor devices. In order to solve the above problems, the prior art provides a solution of replacing the polysilicon gate with a metal gate. [0003] In U.S. Patent No. 6,664,195, a method for forming a metal gate is provided, including: providing a semiconductor substrate, on which a replacement gate structure is formed, and on the semiconductor substrate covering the replacement gate structure. An interlayer dielectric layer; using the replacement gate structure as a stop laye...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/336
Inventor 何永根禹国宾吴兵
Owner SEMICON MFG INT (SHANGHAI) CORP