Unlock instant, AI-driven research and patent intelligence for your innovation.

ldmos transistor manufacturing method

A manufacturing method and transistor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as difficult balance, and achieve the effect of improving breakdown voltage

Active Publication Date: 2015-10-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, a uniformly distributed N-depletion region must strike a balance between the two breakdown voltages, which is difficult to balance

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • ldmos transistor manufacturing method
  • ldmos transistor manufacturing method
  • ldmos transistor manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0014] The manufacturing method of LDMOS transistor is as follows image 3 As shown, in the BCD (Bipolar-CMOS-DMOS) process flow,

[0015] First, an oxide layer is formed over the depletion region of the LDMOS transistor, and a polysilicon field plate is formed over the oxide layer over the depletion region of the LDMOS near the source end;

[0016] Then, impurity ion implantation is performed on the depletion region of the LDMOS transistor, wherein, vertical impurity ion implantation is performed on the depletion region of the LDMOS transistor not covered by the polysilicon field plate, that is, impurity ion implantation at a 0-degree angle is performed; for the polysilicon field plate The depletion region of the covered LDMOS transistor is subjected to oblique ion implantation. The implantation energy of impurity ions implanted by oblique ion implantation is greater than the energy of vertical impurity ion implantation, and the implantation dose of impurity ions implanted by...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a manufacture method of a transistor of a lateral diffused metal-oxide-semiconductor (LDMOS). Firstly, an oxide layer is formed on a depletion region of the transistor of the LDMOS, and a polycrystalline silicon field board is formed above the oxide layer on the depletion region of the LDMOS and at one end close to a source electrode. Then, foreign ions are filled in the depletion region of the transistor of the LDMOS, wherein vertical impurity ion filling is conducted on the area, without covering of the polycrystalline silicon field board, of the depletion region of the transistor of the LDMOS, and oblique-angled ion filling is conducted on the area, covered by the polycrystalline silicon field board, of the depletion region of the transistor of the LDMOS. The invention further discloses the transistor of the LDMOS. According to the transistor of the LDMOS and the manufacture method, breakdown voltage under the conducting state of the transistor of the LDMOS can be improved, and at the same time, descending of the breakdown voltage in the turn-off state can be avoided.

Description

technical field [0001] The present application relates to semiconductor technology, and in particular, to a method for manufacturing an LDMOS transistor. Background technique [0002] In order to improve the static off-state and on-state breakdown voltage of the device, and reduce the on-resistance, RESURF (Reduce SURface Field, reduce the surface electric field) structure, in order to reduce the surface electric field and increase the breakdown voltage. like figure 1 As shown in RESURF structure, the net space charge in the N-depletion region (N_drift) is a key factor, ideally to achieve a concentration such that the N-depletion region is fully depleted vertically and the lateral PN junction The maximum broadening of the depletion region allows the highest breakdown voltage to be achieved. Under high current injection, the net space charge of the N-depletion region is the positive donor ion concentration minus the negative charge concentration of current electrons, so th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/265H01L29/78
Inventor 杨文清张帅
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More