Semiconductor device and manufacturing method
A manufacturing method and semiconductor technology, applied in the manufacture of semiconductor devices and the field of semiconductor devices, can solve the problems of device failure, no impurity diffusion, and high process cost, and achieve the effect of improving reliability.
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Embodiment 1
[0044] Such as Figure 4 As shown, it is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; a semiconductor device according to the present invention is illustrated by taking an IGBT device with a reverse breakdown voltage of 3300V and an N-type drift region as an example. The silicon chip 1 The doping concentration of the N-type impurity is the first impurity concentration C1=1E13CM -3 , The resistivity is 180 ohms. cm. A semiconductor device according to Embodiment 1 of the present invention includes:
[0045] A first P-type region 7 formed on the front side of the silicon wafer. The front process of a semiconductor device in Embodiment 1 of the present invention also includes: a gate oxide 5 and a polysilicon electrode 6 located at the upper end of the silicon wafer 1; an interlayer dielectric film 9 covering the polysilicon electrode 6; formed on the first P The N+ source 8 in the type region 7; the contact hole...
Embodiment 4
[0064] For the manufacturing method of the semiconductor device in the fourth embodiment of the present invention, please refer to the device structure Figure 4 The difference between the method for manufacturing a semiconductor device in Embodiment 4 of the present invention and the method for manufacturing a semiconductor device in Embodiment 1 of the present invention is that steps 1 to 4 of the method in Embodiment 4 of the present invention adopt steps 1 to 4 of the method in Embodiment 1 of the present invention, Step 2 and Step 3 form the first part of the second N-type region 1b; after the front-side process in Step 4, the method of Embodiment 4 of the present invention further includes the following steps:
[0065] Step 5: Perform second hydrogen impurity ion implantation from the back side of the silicon wafer 1; the second hydrogen impurity ion implantation includes multiple implants with different energies, and the implantation energy ranges from 3MEV to 5MEV; a pr...
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