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Semiconductor device and manufacturing method

A manufacturing method and semiconductor technology, applied in the manufacture of semiconductor devices and the field of semiconductor devices, can solve the problems of device failure, no impurity diffusion, and high process cost, and achieve the effect of improving reliability.

Active Publication Date: 2016-02-10
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since Al and other metal materials have been formed on the front of the device before annealing, the annealing temperature generally cannot be higher than 500 degrees Celsius when using ordinary thermal annealing technology, and the implanted field-blocking layer ions are not activated efficiently, and at the same time, they cannot reach the diffusion level. Effect
The use of laser annealing can greatly improve the efficiency, the depth that laser annealing can reach is limited, and the process cost is high, so it is impossible to activate for a long time, and there is no effective diffusion of impurities, so the obtained field blocking layer The ion distribution of the
This dramatic change in carrier concentration, in the process of changing the device from the on state to the off state, due to the large built-in electric field in the field blocking layer, accelerates the flow of electrons in the drift region during the on state. The speed of the N-type field-blocking layer causes a sharp drop in current and reduces the flexibility of the switch. It is easy to generate a high peak voltage under inductive load to make the device invalid; on the other hand, in a short time, the P+N on the back The blocking layer, that is, the PN junction of the P-type emitter 4 and the field blocking layer 3 is prone to cause a large difference between local electrons and holes, and a very high electric field is formed near the junction, which is also easy to cause the device to fail.

Method used

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  • Semiconductor device and manufacturing method
  • Semiconductor device and manufacturing method
  • Semiconductor device and manufacturing method

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Embodiment 1

[0044] Such as Figure 4 As shown, it is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; a semiconductor device according to the present invention is illustrated by taking an IGBT device with a reverse breakdown voltage of 3300V and an N-type drift region as an example. The silicon chip 1 The doping concentration of the N-type impurity is the first impurity concentration C1=1E13CM -3 , The resistivity is 180 ohms. cm. A semiconductor device according to Embodiment 1 of the present invention includes:

[0045] A first P-type region 7 formed on the front side of the silicon wafer. The front process of a semiconductor device in Embodiment 1 of the present invention also includes: a gate oxide 5 and a polysilicon electrode 6 located at the upper end of the silicon wafer 1; an interlayer dielectric film 9 covering the polysilicon electrode 6; formed on the first P The N+ source 8 in the type region 7; the contact hole...

Embodiment 4

[0064] For the manufacturing method of the semiconductor device in the fourth embodiment of the present invention, please refer to the device structure Figure 4 The difference between the method for manufacturing a semiconductor device in Embodiment 4 of the present invention and the method for manufacturing a semiconductor device in Embodiment 1 of the present invention is that steps 1 to 4 of the method in Embodiment 4 of the present invention adopt steps 1 to 4 of the method in Embodiment 1 of the present invention, Step 2 and Step 3 form the first part of the second N-type region 1b; after the front-side process in Step 4, the method of Embodiment 4 of the present invention further includes the following steps:

[0065] Step 5: Perform second hydrogen impurity ion implantation from the back side of the silicon wafer 1; the second hydrogen impurity ion implantation includes multiple implants with different energies, and the implantation energy ranges from 3MEV to 5MEV; a pr...

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Abstract

The invention discloses a semiconductor device. A graded region is arranged in a drift region of the semiconductor device, the doping concentration of the graded region increases slowly, the graded region is located on one side of the back face of a silicon wafer, and the doping concentration of the graded region is larger than the doping concentration of a uniform region. The highly doping graded region can ensure lower on resistance obtained by the semiconductor device, and at the same time, the velocity of increase of the doping concentration of the graded region is controlled well, the defect that a built-in electric field in a filed blocking layer is large in an existing filed blocking-type semiconductor device is overcome, accordingly a current dropping speed of the semiconductor device can be effectively controlled when the semiconductor device is cut off, and reliability of the device can be improved. The invention further discloses a manufacturing method of the semiconductor device.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a semiconductor device; the invention also relates to a method for manufacturing the semiconductor device. Background technique [0002] In semiconductor high-voltage devices, whether it is an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), or a MOSFET, when the gate of the device is positively biased, the device is turned on. The power consumption is the smallest, that is, the on-state voltage drop of the device is expected to be small, and the on-state voltage drop of the device can be directly reduced by using a thinner silicon chip, but the decrease in the thickness of the device will reduce the reverse breakdown of the device. Under the condition of pressure resistance, the two are a pair of contradictions. In order to solve the above contradictions, the field blocking layer is introduced into the semiconductor high-volta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L29/06H01L21/331
Inventor 肖胜安钱文生朱东园
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP