nldmos structure compatible with 5 volt cmos process and its fabrication method

Abstract

The invention discloses an N-type laterally diffused metal oxide semiconductor (NLMOS) structure compatible with a 5-V complementary metal oxide semiconductor (CMOS) process and a manufacturing method thereof. The structure comprises a field oxygen area, a polycrystalline silicon grid, a grid oxidizing layer, an isolation lateral wall and a source drain, wherein the field oxygen area, the polycrystalline silicon grid, the grid oxidizing layer, the isolation lateral wall and the source drain are formed through the 5-V CMOS process in compatible mode. The structure further comprises a P-type base area formed by a P trap in the CMOS process and an N drifting area formed by an N trap in the CMOS process. The manufacturing method includes: 1) using the P trap as the P-type base area and the N trap as the N drifting area; 2) controlling the distance between the P-type base area and the N drifting area; 3) shortening the length of an accumulation area to -0.2-0.1mum; and 4) finishing manufacturing of the field oxygen area, the polycrystalline silicon grid, the grid oxidizing layer, the isolation lateral wall, the source drain and electrodes in connection mode according to the 5-V CMOS process. By means of the structure and the method, breakdown voltage can reach over 25V, and use requirements of switching devices and simulation devices can be met.

Description

technical field [0001] The invention relates to an NLDMOS (N-type lateral double-diffused metal oxide semiconductor) structure and a manufacturing method thereof, in particular to an NLDMOS structure compatible with a 5-volt CMOS (complementary metal oxide semiconductor) process and a manufacturing method thereof. Background technique [0002] DMOS (Double Diffused Metal Oxide Semiconductor) is currently widely used in power management circuits due to its high voltage resistance, high current drive capability and extremely low power consumption. In the BCD (Bipolar-CMOS-DMOS) process, although DMOS and CMOS are integrated in the same chip, due to the requirements of high withstand voltage and low on-resistance, the conditions of the background area and drift area of ​​DMOS are often not comparable to those of CMOS. Existing process conditions are shared. The main reason is that in the case of high withstand voltage, DMOS needs the doping of the drift region to be light, so ...

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Problems solved by technology

In the BCD (Bipolar-CMOS-DMOS) process, although DMOS and CMOS are integrated in the same chip, due to the requirements of high withstand voltage and low on-resistance, the conditions of the background area and drift area of ​​DMOS are often not comparable to those of CMOS. Existing process conditions sharing

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