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Lead welding disc leading-out method for wafer level packaging

A wafer-level packaging and pad technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of inconvenient operation, increased slivers, waste of leads, etc., to reduce the risk of chip damage to the chip, Simple manufacturing process and the effect of improving production efficiency

Active Publication Date: 2013-09-18
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, holes are also drilled through the cover plate on the front of the pads to expose the pads, and the leads pass through the connection pads from the cover plate. The leads of this method are too long, which is inconvenient to operate and causes waste of leads.
The lead pad lead-out method of wafer-level packaging in the prior art usually uses manual splitting, which will increase the risk of chip damage by splitting

Method used

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  • Lead welding disc leading-out method for wafer level packaging

Examples

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Comparison scheme
Effect test

Embodiment 1

[0028] Embodiment 1. There is no limitation on the material of the cover plate in the above method. If the cover plate is glass, the shallow groove can be etched and processed by wet etching. The specific process steps are as follows:

[0029] (1a), the metal thin film is prepared on the glass substrate by evaporation or sputtering

[0030] (2a), photolithography, etch the metal film to form a metal mask pattern for the next step of etching the glass

[0031] (3a), using the patterned metal thin film as a mask, using a glass etching solution to perform isotropic wet etching on the glass cover plate, thereby forming shallow grooves;

Embodiment 2

[0032] Embodiment 2, if the glass cover plate, the silicon cover plate can etch the shallow grooves in addition to the above-mentioned wet etching method, the dry etching technology can also be used to etch the shallow grooves. The process steps include: The resist is used as a mask, and shallow trenches are prepared using DRIE dry etching equipment.

Embodiment 3

[0033] Embodiment 3, in addition to using the above methods to etch and process shallow grooves, it is also possible to use mechanical processing methods, that is, use a dicing machine or an engraving machine to process shallow grooves with controllable depth on the upper cover;

[0034] Using the lead pad lead-out method of the wafer-level package above, the lead wire can be easily and conveniently drawn out from the pad, the manufacturing process is simple, and the lead wire distance is short, the anodic bonding process technology is mature, and the bonding strength is high. The chip separation is completed on the dicing machine, without manual splitting, which reduces the risk of chip damage by splitting.

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PUM

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Abstract

The invention provides a lead welding disc leading-out method for wafer level packaging. By the method, a lead can be led out from a welding disc simply and conveniently, manufacturing process is simple, and the needed lead is not too long, so that production efficiency is improved, production cost is greatly lowered, and the risk of damaging of a chip caused by wafer cracking when the lead is led out is lowered. The method is characterized by including the following steps: (1), etching a shallow groove at a position, corresponding to the welding disc, on a cover plate; (2), covering and bonding the cover plate on a wafer with the welding disc; (3), performing staggered cutting to the cover plate and the wafer which are formed integrally to expose the covered welding disc connected with the lead, and leading out the welding disc through the lead, wherein a shallow groove face on the cover plate and the wafer are connected and form a space.

Description

technical field [0001] The invention relates to the technical field of substrate packaging in the microelectronics industry, in particular to a method for leading out lead pads of wafer-level packaging. Background technique [0002] With the development of microelectronics technology, the processing functions of microelectronics are complex and diversified. During the processing of chip substrates, chip substrates are usually packaged. In the process of wafer level packaging, the front side needs to be hermetically sealed or covered The chip protected by the board is led out from the pad after packaging. In traditional wafer-level hermetic packaging, the front side of the chip is protected by a cover plate regardless of the wafer-level bonding method (anodic bonding, eutectic bonding, polymer bonding, diffusion bonding, etc.) Up, so the front pad of the chip must be led out. [0003] Among the existing lead pad lead-out methods for wafer-level packaging, the more advanced ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60
Inventor 耿菲
Owner NAT CENT FOR ADVANCED PACKAGING