Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Micro-pore electroplated copper filling method for three-dimensional (3D) copper interconnection high aspect ratio through-silicon-via technology

A high-aspect-ratio, through-silicon via technology, applied in circuits, electrical components, electrolytic processes, etc., can solve problems such as holes left in the channel, and achieve the effect of easy maintenance and simple formula

Inactive Publication Date: 2013-10-23
SHANGHAI SINYANG SEMICON MATERIALS
View PDF6 Cites 38 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the deposition rate in the upper part of the channel is faster than that in the lower part, holes will inevitably be left in the channel

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Micro-pore electroplated copper filling method for three-dimensional (3D) copper interconnection high aspect ratio through-silicon-via technology
  • Micro-pore electroplated copper filling method for three-dimensional (3D) copper interconnection high aspect ratio through-silicon-via technology
  • Micro-pore electroplated copper filling method for three-dimensional (3D) copper interconnection high aspect ratio through-silicon-via technology

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] Take the 10×100μm hole pattern as an example.

[0045] Pretreatment conditions: under the condition of vacuum degree of 0~0.2 torr (torr), vacuumize for 5 minutes, soak in pure water for 1-10 minutes.

[0046] Proportion of copper methanesulfonate basic plating solution: 100g / L Cu 2+ , 30g / L ultra-pure methanesulfonic acid, and 30mg / L Cl - .

[0047] The additive ratio is accelerator: inhibitor: leveler=5:10:5.

[0048] Experimental conditions: temperature = 25 ℃, flow rate = 15 L / min, cathode rotation speed = 50 RPM.

[0049] Electroplating parameters: 0.01ASD 120s; 0.1ASD 600s; 0.4ASD 3000s.

[0050] Result: if image 3 As shown, it is completely filled, without defects, and the surface copper thickness is <3μm.

Embodiment 2

[0052] Take the 15×150μm hole pattern as an example.

[0053] Pretreatment conditions: under the condition of vacuum degree of 0~0.2 torr, vacuumize for 5 minutes, soak in pure water for 1-10 minutes.

[0054] Proportion of copper methanesulfonate basic plating solution: 90g / L Cu 2+ , 20g / L of ultra-pure methanesulfonic acid, and 20mg / L of Cl - .

[0055] The additive ratio is accelerator:inhibitor:leveler=3:10:7.

[0056] Experimental conditions: temperature=22-25 ℃, flow rate=15 L / min, rotation speed=50 RPM.

[0057] Plating parameters: 0.01ASD 120s; 1.0ASD 300s; 0.7ASD 600s; 0.5ASD 2400s; 0.7ASD 300s; 0.3ASD 1200s.

[0058] Result: if Figure 4 As shown, completely filled with no defects.

[0059] Post-plating treatment: Rinse the wafer with deionized water for 2 minutes and dry it.

[0060] The electroplating samples of embodiment one and embodiment two gained are analyzed and tested and evaluated:

[0061] 1. Cross-section analysis: Slice the electroplated sample ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
pore sizeaaaaaaaaaa
depthaaaaaaaaaa
aspect ratioaaaaaaaaaa
Login to View More

Abstract

The invention discloses a micro-pore electroplated copper filling method for a three-dimensional (3D) copper interconnection high aspect ratio through-silicon-via technology. The micro-pore electroplated copper filling method comprises the following steps of: 1, preparing an electroplating solution of a copper methane sulfonate system; 2, wetting micro pores of the through-silicon-via technology through electroplating pretreatment; 3, electrifying and slotting, and increasing the ultralow current diffusion step, so that the copper ion and additives are reasonably distributed on the surfaces and inside the micro pores through the through-silicon-via technology; 4, connecting a silicon wafer where the through-silicon-via technology is positioned with a cathode of a power supply, so that the electroplating surface of the wafer is completely soaked in the electroplating solution, step-by-step current electroplating is performed under the condition that the cathode is rotated or stirred, and the electroplating conditions comprise the current density of 0.01-10A / dm<2> and the temperature of 15-30 DEG C; and 5, completely and thoroughly washing the wafer by using deionized water, performing spin-dry or blow-dry. The provided micro-pore electroplated copper filling method for the 3D copper interconnection high aspect ratio through-silicon-via technology is high in pore filling speed and thin in surface copper, hole and crack risks are avoided, and complete filling of high-difficulty hole with the depth-to-width ratio of more than 10:1 can be realized.

Description

technical field [0001] The invention relates to a step-by-step electroplating method for micropore copper plating suitable for 3D through-silicon via technology, in particular to a micropore electroplating copper filling method for 3D copper interconnection high aspect ratio through-silicon via technology. Background technique [0002] Through-silicon via technology (TSV, Through-Silicon-Via) is the latest technology to realize the interconnection between chips by making vertical conduction between chips and between wafers and wafers. Different from the previous IC package bonding and overlay technology using bumps, TSV can maximize the density of chips stacked in three dimensions, minimize the size of the chip, and greatly improve the speed of chip operation and reduce power consumption. [0003] Since the copper electroplating deposition process is well established in semiconductor process technology, it is believed that this process can be easily changed from copper damas...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): C25D7/04C25D7/12C25D3/38C25D21/12
CPCC25D3/38C25D7/12H01L21/2885H01L21/76898C25D5/34C25D5/48H01L21/76879H01L21/76883
Inventor 王溯于仙仙马丽李艳艳
Owner SHANGHAI SINYANG SEMICON MATERIALS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com