Manufacturing method for two-layer silicon epitaxial wafer used for bipolar transistor

A technology of bipolar transistors and silicon epitaxial wafers, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as double breakdown and abnormal junction characteristics

Active Publication Date: 2013-10-23
HEBEI POSHING ELECTRONICS TECH
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Problems solved by technology

In addition, in the production of high-resistance epitaxial wafers, if the content of inversion impurities in the substrate is high and the contamination of inversion impurities in the process is serious, the epitaxial layer often produces interlayers, which makes the junction characteristics abnormal and the reverse breakdown characteristic curve appears. "Step" or double breakdown phenomenon

Method used

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Embodiment Construction

[0012] A method for manufacturing a double-layer silicon epitaxial wafer for bipolar transistors, comprising the following steps: (1) Growth of the first layer of silicon epitaxial wafer: Although HCl corrosion at high temperature is beneficial to improving the lattice structure, it will also produce some By-products, and a layer of substrate surface is peeled off at high temperature, so some of these by-products and impurities in the substrate also enter the atmosphere. In order to ensure the quality of the crystal lattice, the polishing temperature should be appropriately increased, generally set at 1170°C-1190°C. In order to reduce the volatilization of substrate impurities, it is necessary to reduce the polishing amount, and choose to remove the polishing amount of 0.1-0.2 μm. The first layer is a high-concentration epitaxial layer. The high-concentration epitaxial layer is prone to condensation and nucleation of dopants, and the surface becomes foggy. Therefore, the proc...

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Abstract

The invention discloses a manufacturing method for a two-layer silicon epitaxial wafer used for a bipolar transistor. Compared with a manufacturing method for a conventional two-layer silicon epitaxial wafer, the manufacturing method for the two-layer silicon epitaxial wafer used for the bipolar transistor is characterized by comprising the following steps of removing micro damages of the surface of a silicon wafer by using a hydrogen chloride (HCl) polishing process before a first layer silicon epitaxial wafer is grown; taking out the silicon wafer after the first layer silicon epitaxial wafer is grown to perform etching treatment on a system; and cleaning the silicon wafer before a second layer is grown to ensure the surface to be clean, removing the micro damages of the surface by using the HCl polishing process, and removing impurities by using hydrogen (H2) after polishing. According to the manufacturing method, a reaction chamber etching step is inserted, and therefore, the uniformity and the repeatability of the electrical resistivity of an epitaxial layer are ensured, and the performance and the finished product rate of a device are ensured.

Description

technical field [0001] The present invention relates to the technical field of manufacturing methods of semiconductor devices or other components, in particular to a manufacturing method of double-layer silicon epitaxial wafers. Background technique [0002] For bipolar transistors, breakdown voltage and large current linear range are a pair of contradictory electrical parameters. In order to increase the breakdown voltage, the method of increasing the resistivity of the silicon epitaxial material is usually adopted, but this will also lead to a decrease in the linear range of large currents at the same time. Especially in the production of ultra-high frequency power devices is particularly prominent. In addition, in the production of high-resistance epitaxial wafers, if the content of inversion impurities in the substrate is high and the contamination of inversion impurities in the process is serious, the epitaxial layer often produces interlayers, which makes the junction...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8222
Inventor 袁肇耿薛宏伟赵丽霞田中元许斌武李永辉侯志义
Owner HEBEI POSHING ELECTRONICS TECH
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