Semiconductor element, semiconductor package structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems affecting bonding effects, heat dissipation effects, and high temperature
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[0017] refer to figure 1 , shows a schematic cross-sectional view of an embodiment of the semiconductor package structure of the present invention. The semiconductor package structure 1 includes a substrate 12 , a semiconductor element 10 and a heat sink 20 . The substrate 12 is a packaging substrate, which includes a first surface 121 , a second surface 122 and several internal electrical connection elements (not shown in the figure). The internal electrical connection elements are used to electrically connect the first surface 121 and the second surface 122 .
[0018] The semiconductor device 10 includes a semiconductor die 14 , several bumps 15 , a back side metallization (BSM) 16 and a thermal interface material 18 .
[0019] The semiconductor die 14 includes a first surface 141 and a second surface 142 .
[0020] The bumps 15 are located on the first surface 141 of the semiconductor die 14 and electrically connect the first surface 141 of the semiconductor die 14 to th...
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