25Gbps data clock restoring circuit based on edge linearization technique

Abstract

The invention belongs to the technical field of communications, and particularly relates to a 25Gbps data clock restoring circuit based on the edge linearization technique. The circuit comprises a charge pump, a voltage-controlled oscillator, a loop filter, an injection locking frequency divider and a phase discriminator adopting edge linearization. A 12.5GHz differential clock is generated by the voltage-controlled oscillator, and an eight-phase 6.25GHz clock is generated through frequency division of the injection locking frequency divider and delay of an adjustable delay unit; the phase discriminator carries out oversampling on data through the eight-phase clock and controls the charge pump to generate a pulse current through synchronization and logical operation; after being filtered by the loop filter, the pulse current controls the control end of the voltage-controlled oscillator. By means of the 25Gbps data clock restoring circuit, four 6.25Gbps data and corresponding clocks can be generated through 25Gbps input data with low power consumption, and the requirement for good jitter performance and good locking features can be met as well.

Description

Technical field [0001] The invention belongs to the field of communication technology, and specifically relates to a data clock recovery circuit. Background technique [0002] With the continuous increase in the number of people and various portable devices, the amount of data transmission on the communication link has increased exponentially, which has sharply increased the speed and reliability requirements of wired communication systems, especially data centers. Therefore, as the core of data center communication technology, optical fiber communication and high-speed wired communication also need to be greatly improved in speed, power consumption and reliability. As the most important part of the receiving end of optical fiber communication and high-speed wired communication, the data clock recovery circuit determines the quality of the receiving end clock of the entire system and the jitter and bit error rate of the recovered data. [0003] The traditional high-speed data cloc...

AI Technical Summary

Problems solved by technology

However, the recovery data and clock jitter performance of the linear data clock recovery circuit is better, but the requirements for the logic circuit and the charge pump in the phase detector are higher, and the lock time is longer. The lock time of the Bang-bang data clock recovery circuit It is short, but the jitter performance is poor. Therefore, it is also a challenging job to include the advantages of these two structures and get rid of their disadvantages to achieve a perfect compromise.

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