A kind of preparation method of semiconductor device

Abstract

The invention relates to a preparation method of a semiconductor device; the method comprises the steps of providing a semiconductor substrate at least having a grid electrode structure; forming grooves on two sides of the grid electrode and epitaxially growing a SiGe layer in the grooves; carrying out low energy P type doping for the SiGe layer on two sides of the grid electrode so as to form a source drain zone, thereby reducing contact resistance. The preparation method of the semiconductor device is provided, in order to reduce various contact resistances in a PMOS, low energy doping is carried out in forming the PMOS source drain zone, such as low energy ion injection or plasma doping are carried out, and a source drain injection step is omitted; the doping is carried out after the SiGe layer is epitaxially formed, wherein the SiGe layer may be a composite layer; the method can further reduce the size of silicide, and can better keep crushing stress in the PMOS zone, can reduce the stress relaxation and contact resistance on the source drain, thereby further improving performance of the device.

Description

technical field [0001] The invention relates to the field of semiconductors, and in particular, the invention relates to a method for preparing a semiconductor device. Background technique [0002] With the continuous development of integrated circuit technology, more devices will be integrated on the chip, and the chip will adopt faster speed. Driven by these requirements, the geometric size of devices will continue to shrink, and new materials, new technologies and new manufacturing processes will be continuously used in the chip manufacturing process. At present, the preparation of semiconductor devices has been developed to the nanometer level, and the preparation process of conventional devices has gradually matured. [0003] At present, in order to obtain better performance in the process of preparing CMOS for semiconductor devices, epitaxial e-SiGe is usually carried out in the source and drain regions of CMOS to apply compressive stress to the channel of the substra...

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Problems solved by technology

[0003] At present, in order to obtain better performance in the process of preparing CMOS for semiconductor devices, epitaxial e-SiGe is usually carried out in the source and drain regions of CMOS to apply compressive stress to the channel of the substrate to improve the performance of PMOS. Form a recess on the PMOS source and drain, and then grow e-SiGe epitaxially, but there are many challenges in the process of forming e-SiGe, such as integration, defect control, selectivity, etc., the biggest problem is in When forming the concave epitaxial growth, the increase of the thickness of the epitaxial layer and the increase of the Ge content in the epitaxial layer cause stress relaxation on the source and drain regions, especially when the size of the PMOS device is reduced to 32nm level, the strain Relaxation (stressrelaxation) will directly lead to the reduction of device performance

[0004] In addition, ion implantation is usually performed after epitaxial SiGe, and doping is performed to obtain a higher doping concentration. Form a doping tail profile to reduce the leakage at the junction, or perform B (Boron) doping on the source and drain while epitaxially growing SiGe, and adjust the gas flow and other parameters to achieve sufficient However, after ion implantation or in-situ doping in the source and drain of PMOS SiGe, the device will usually cause strain relaxation after annealing, and the strain relaxation will directly lead to the reduction of device performance.

In the existing method, there is in-situ doping of B to eliminate strain relaxation, but the effect is not ideal. At the same time, the resistance at the interface of the device prepared by the above method also becomes a big problem when the electrical connection is formed. For example, in The resistance between the contact plug and the source-drain, and the resistance between the epitaxial layer and the ion-implanted section, etc.

[0005] Therefore, the current method cannot completely eliminate the source-drain relaxation caused by ion implantation, and the contact resistance on the source-drain is also very large, which affects the performance of the device. It is necessary to improve the existing technology to eliminate the impact

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